Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
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High-level synthesis under multi-cycle interconnect delay

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913385 ◽

2002 ◽

Author(s):

Jinhwan Jeon ◽

Daehong Kim ◽

Dongwan Shin ◽

Kiyoung Choi

Keyword(s):

High Level Synthesis ◽

Interconnect Delay ◽

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Post-layout transistor sizing for power reduction in cell-based design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913333 ◽

2002 ◽

Author(s):

M. Hashimoto ◽

H. Onodera

Keyword(s):

Power Reduction ◽

Transistor Sizing

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Reducing bus delay in submicron technology using coding

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913289 ◽

2002 ◽

Author(s):

P.P. Sotiriadis ◽

A. Chandrakasan

Keyword(s):

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Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913383 ◽

2002 ◽

Author(s):

A. Kitajima ◽

M. Itoh ◽

J. Sato ◽

A. Shiomi ◽

Y. Takeuchi ◽

...

Keyword(s):

Design System ◽

Pipelined Processors

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Coarse grain reconfigurable architectures

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913368 ◽

2002 ◽

Author(s):

R. Hartenstein

Keyword(s):

Reconfigurable Architectures ◽

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An optimum fitting algorithm for generation of reduced-order models

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913306 ◽

2002 ◽

Author(s):

M.M. Gourary ◽

S.G. Rusakov ◽

S.L. Ulyanov ◽

M.M. Zharov ◽

B.J. Mulvaney

Keyword(s):

Reduced Order Models ◽

Reduced Order ◽

Fitting Algorithm

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A real-time 64-monosyllable recognition LSI with learning mechanism

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913274 ◽

2002 ◽

Author(s):

K. Nakamura ◽

Qiang Zhu ◽

S. Maruoka ◽

T. Horiyama ◽

S. Kimura ◽

...

Keyword(s):

Real Time ◽

Learning Mechanism

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A vector-pipeline DSP for low-rate videophones

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913259 ◽

2002 ◽

Author(s):

K. Kobayashi ◽

M. Eguchi ◽

T. Iwahashi ◽

T. Shibayama ◽

X. Li ◽

...

Keyword(s):

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VLSI block placement using less flexibility first principles

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913374 ◽

2002 ◽

Author(s):

Sheqin Dong ◽

Xianlong Hong ◽

Youliang Wu ◽

Yizhou Lin ◽

Jun Gu

Keyword(s):

First Principles ◽

Block Placement

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Provably good global buffering by multiterminal multicommodity flow approximation

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913291 ◽

2002 ◽

Author(s):

F.F. Dragan ◽

A.B. Kahng ◽

I. Mandoiu ◽

S. Muddu ◽

A. Zelikovsky

Keyword(s):

Multicommodity Flow ◽

Flow Approximation

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