Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
Latest Publications

TOTAL DOCUMENTS

129

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780366336

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

An optimum fitting algorithm for generation of reduced-order models

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913306 ◽

2002 ◽

Author(s):

M.M. Gourary ◽

S.G. Rusakov ◽

S.L. Ulyanov ◽

M.M. Zharov ◽

B.J. Mulvaney

Keyword(s):

Reduced Order Models ◽

Reduced Order ◽

Fitting Algorithm

A real-time 64-monosyllable recognition LSI with learning mechanism

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913274 ◽

2002 ◽

Author(s):

K. Nakamura ◽

Qiang Zhu ◽

S. Maruoka ◽

T. Horiyama ◽

S. Kimura ◽

...

Keyword(s):

Real Time ◽

Learning Mechanism

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913383 ◽

2002 ◽

Cited By ~ 6

Author(s):

A. Kitajima ◽

M. Itoh ◽

J. Sato ◽

A. Shiomi ◽

Y. Takeuchi ◽

...

Keyword(s):

Design System ◽

Pipelined Processors

Coarse grain reconfigurable architectures

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913368 ◽

2002 ◽

Cited By ~ 22

Author(s):

R. Hartenstein

Keyword(s):

Reconfigurable Architectures ◽

Coarse Grain

High-level synthesis under multi-cycle interconnect delay

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913385 ◽

2002 ◽

Author(s):

Jinhwan Jeon ◽

Daehong Kim ◽

Dongwan Shin ◽

Kiyoung Choi

Keyword(s):

High Level Synthesis ◽

Interconnect Delay ◽

High Level

Post-layout transistor sizing for power reduction in cell-based design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913333 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Hashimoto ◽

H. Onodera

Keyword(s):

Power Reduction ◽

Transistor Sizing

Reducing bus delay in submicron technology using coding

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913289 ◽

2002 ◽

Cited By ~ 42

Author(s):

P.P. Sotiriadis ◽

A. Chandrakasan

Keyword(s):

Bus Delay

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913378 ◽

2002 ◽

Author(s):

Youngtae Kim ◽

Taewhan Kim

Keyword(s):

Trade Offs ◽

Carry Save Adders

A prototype chip of multicontext FPGA with DRAM for virtual hardware

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913267 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Kawakami ◽

Y. Shibata ◽

H. Amano

A vector-pipeline DSP for low-rate videophones

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) ◽

10.1109/aspdac.2001.913259 ◽

2002 ◽

Author(s):

K. Kobayashi ◽

M. Eguchi ◽

T. Iwahashi ◽

T. Shibayama ◽

X. Li ◽

...

Keyword(s):

Low Rate

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An optimum fitting algorithm for generation of reduced-order models

A real-time 64-monosyllable recognition LSI with learning mechanism

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Coarse grain reconfigurable architectures

High-level synthesis under multi-cycle interconnect delay

Post-layout transistor sizing for power reduction in cell-based design

Reducing bus delay in submicron technology using coding

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

A prototype chip of multicontext FPGA with DRAM for virtual hardware

A vector-pipeline DSP for low-rate videophones

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
Latest Publications