Design of Parity Preserving Reversible DIF-FFT using 90nm Technology

Reduction of power consumption is the major goal in modern circuit design. Reversible logic gate do not lose any information & thus have zero power dissipation. In all signal processing applications, the most important computation involved is Fast Fourier Transform (FFT). For the fault tolerance computation parity preserving logic can be used .The authors present an efficient parity preserving reversible DIF-FFT using 90nm technology. The implementation involves the design of DIF-FFT with reversible P2RG along with Fredkin gate over different combinations of adders (Carry look ahead adder (CLA), Carry save adders (CSA), Carry skip adder (CSK) & Ripple carry adder (RCA)) & multipliers (Array Multiplier (AM), Carry Save Multiplier (CM), Parallel Multiplier (PM), Wallace Tree Multiplier (WM)). DIF-FFT Architectures of different combinations were coded using Verilog & the same was simulated by Modelsim 6.3f. Parameters such as Hardware Device utilization & Power analysis were done using Quartus II 9.0 with respect to Stratix II device which works on 90nm technology. It was found that DIF-FFT Architecture designed using CSA & CM uses lesser resource utilization whereas architecture designed using CSA & AM has lesser Power dissipation by 72% & 81% respectively.

Design of Fast Efficient Radix-16 Sequential Multiplier

Multiplication is an important function in computer arithmetic operations. The multiplication process will be done by the shift-and-add sequential multiplication procedure. Radix-16 sequential multiplier design generates the radix-16 partial products as two low (L) and high (H) components. In order to reduce cycle time, Brent-Kung adder and two radix 16 carry-save adders are used to generate radix-16 partial products. The proposed design of radix-16 sequential multiplier is efficient over previous designs and comparison depicts ADP and PDP of existing method are 11.22% and 8.45% than proposed method. However, the Excess area-Delay product and Excess-power-Delay product is also lowered. The design is carried out in Xilinx ISE 14.5 software and cadence tool for simulation and synthesis results. Fast efficient radix-16 sequential multiplier can be used in many digital signal processing applications

Implementation of time efficient hybrid multiplier for FFT computation

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.

RADIX-10 PARALLEL DECIMAL MULTIPLIER

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a new algorithm decimal multioperand carry-save addition that uses a unconventional decimal-coded number systems. We further detail these techniques and it significantly improves the area and latency of the previous design, which include: optimized digit recoders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters.

AN EFFICIENT REVERSE CONVERTER FOR THE NEW FOUR-MODULI SET {22n, 2n+1 - 1, 2n/2 + 1, 2n/2 - 1}

In this paper, the new four-moduli set {22n, 2n+1 - 1, 2n/2 + 1, 2n/2 - 1} for even n is introduced. This moduli set has 4n-bit dynamic range and well-formed moduli which result in increased performance of RNS arithmetic unit. Then, an efficient reverse converter is presented based on New Chinese remainder theorem2 (New CRT-II) for proposed moduli set. The converter is ROM-free and based on carry save adders and modular adders which can be efficiently implemented by VLSI circuits. The presented reverse converter for moduli set {22n, 2n+1 - 1,2n/2 + 1, 2n/2 - 1} has lower delay and hardware cost in comparison to the reverse converter of the latest introduced four-moduli set {2n - 1, 2n, 2n + 1, 2n+1 - 1} with 4n-bit dynamic range.