[1992] Proceedings The European Conference on Design Automation
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94

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Published By IEEE Comput. Soc. Press

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Energy minimization based delay testing

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205939 ◽

2003 ◽

Author(s):

S.T. Chakradhar ◽

M.A. Iyer ◽

V.D. Agrawal

Keyword(s):

Energy Minimization ◽

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An automatic layout generator for analog circuits

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205989 ◽

2003 ◽

Author(s):

J.D. Conway ◽

G.G. Schrooten

Keyword(s):

Analog Circuits ◽

Automatic Layout

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Solving the path sensitization problem in linear time

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205959 ◽

2003 ◽

Author(s):

P. Altenbernd ◽

J. Strathaus

Keyword(s):

Linear Time ◽

Path Sensitization

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A new approach for checking the unique state coding property of signal transition graphs

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205945 ◽

2003 ◽

Author(s):

Meng-Lin Yu ◽

P.A. Subrahmanyam

Keyword(s):

New Approach ◽

Transition Graphs

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Flow-a concurrent methodology manager

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205885 ◽

2003 ◽

Author(s):

Y. Kashai

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Accurate delay models for ECL logic synthesis

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205901 ◽

2003 ◽

Author(s):

R. Makowitz ◽

A. Wild

Keyword(s):

Logic Synthesis ◽

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Improved port assignment on channel boundaries

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205949 ◽

2003 ◽

Author(s):

E. Levin

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Multicell quad trees

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205911 ◽

2003 ◽

Author(s):

S.J. Su ◽

Y.S. Kuo

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Functional decomposition for universal logic cells using substitution

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205889 ◽

2003 ◽

Author(s):

F. Dresig ◽

Ph. Lanches ◽

O. Rettig ◽

U.G. Baitinger

Keyword(s):

Universal Logic ◽

Functional Decomposition ◽

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A parallel hierarchical design rule checker

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205910 ◽

2003 ◽

Author(s):

N. Hedenstierna ◽

K.O. Jeppson

Keyword(s):

Design Rule ◽

Hierarchical Design

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