[1992] Proceedings The European Conference on Design Automation
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Published By IEEE Comput. Soc. Press

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Solving the path sensitization problem in linear time

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205959 ◽

2003 ◽

Cited By ~ 3

Author(s):

P. Altenbernd ◽

J. Strathaus

Keyword(s):

Linear Time ◽

Path Sensitization

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Energy minimization based delay testing

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205939 ◽

2003 ◽

Cited By ~ 17

Author(s):

S.T. Chakradhar ◽

M.A. Iyer ◽

V.D. Agrawal

Keyword(s):

Energy Minimization ◽

Delay Testing

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An automatic layout generator for analog circuits

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205989 ◽

2003 ◽

Cited By ~ 19

Author(s):

J.D. Conway ◽

G.G. Schrooten

Keyword(s):

Analog Circuits ◽

Automatic Layout

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Design automation of power integrated circuits in EDGE environment

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205933 ◽

2003 ◽

Cited By ~ 2

Author(s):

L. Hebrard ◽

G. Jacquemod ◽

B. Boutherin ◽

M. Le Helley

Keyword(s):

Integrated Circuits ◽

Design Automation

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Space-efficient extraction algorithms

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205990 ◽

2003 ◽

Cited By ~ 5

Author(s):

N.P. van der Meijs ◽

A.J. van Genderen

Keyword(s):

Efficient Extraction

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A new approach for checking the unique state coding property of signal transition graphs

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205945 ◽

2003 ◽

Cited By ~ 2

Author(s):

Meng-Lin Yu ◽

P.A. Subrahmanyam

Keyword(s):

New Approach ◽

Transition Graphs

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Flow-a concurrent methodology manager

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205885 ◽

2003 ◽

Cited By ~ 2

Author(s):

Y. Kashai

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Accurate delay models for ECL logic synthesis

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205901 ◽

2003 ◽

Author(s):

R. Makowitz ◽

A. Wild

Keyword(s):

Logic Synthesis ◽

Delay Models

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Improved port assignment on channel boundaries

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205949 ◽

2003 ◽

Cited By ~ 1

Author(s):

E. Levin

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Multicell quad trees

[1992] Proceedings The European Conference on Design Automation ◽

10.1109/edac.1992.205911 ◽

2003 ◽

Author(s):

S.J. Su ◽

Y.S. Kuo

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[1992] Proceedings The European Conference on Design AutomationLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Solving the path sensitization problem in linear time

Energy minimization based delay testing

An automatic layout generator for analog circuits

Design automation of power integrated circuits in EDGE environment

Space-efficient extraction algorithms

A new approach for checking the unique state coding property of signal transition graphs

Flow-a concurrent methodology manager

Accurate delay models for ECL logic synthesis

Improved port assignment on channel boundaries

Multicell quad trees

[1992] Proceedings The European Conference on Design Automation
Latest Publications