Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97

2002 ◽

Cited By ~ 1

Author(s):

A. Biancardi ◽

V. Cantoni ◽

D. Codega ◽

M. Pini

Keyword(s):

Interactive Tool

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A parallelizing method for implementing image processing tasks on SIMD linear processor arrays

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631944 ◽

2002 ◽

Cited By ~ 8

Author(s):

S. Kyo ◽

S. Okazaki ◽

Y. Fujita ◽

N. Yamashita

Keyword(s):

Image Processing ◽

Processor Arrays

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A scalable architecture for low and intermediate level image processing

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.632042 ◽

2002 ◽

Author(s):

J.G.E. Olk ◽

P.P. Jonker

Keyword(s):

Image Processing ◽

Intermediate Level ◽

Scalable Architecture

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External loop unrolling of image processing programs: optimal register allocation for RISC architectures

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631891 ◽

2002 ◽

Cited By ~ 2

Author(s):

N. Zingirian ◽

M. Maresca

Keyword(s):

Image Processing ◽

Register Allocation ◽

Loop Unrolling ◽

External Loop

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Vision chip architecture using general-purpose processing elements for 1 ms vision system

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.632052 ◽

2002 ◽

Cited By ~ 37

Author(s):

T. Komuro ◽

I. Ishii ◽

M. Ishikawa

Keyword(s):

Vision System ◽

General Purpose ◽

Vision Chip ◽

Processing Elements

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Making a dataparallel language portable for massively parallel array computers

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631935 ◽

2002 ◽

Cited By ~ 7

Author(s):

M.C. Herbordt ◽

J.H. Burrill ◽

C.C. Weems

Keyword(s):

Massively Parallel ◽

Parallel Array

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Asynchronous SIMD: an architectural concept for high performance image processing

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.632024 ◽

2002 ◽

Cited By ~ 1

Author(s):

C. Weems

Keyword(s):

Image Processing ◽

High Performance

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Page segmentation using a pyramidal architecture

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631950 ◽

2002 ◽

Cited By ~ 2

Author(s):

V. Cantoni ◽

L. Lombardi ◽

G. Manzini ◽

L. Cinque

Keyword(s):

Page Segmentation

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Analog sensor processing using exposure control. A new concept for high speed image processing

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631894 ◽

2002 ◽

Author(s):

A. Astrom ◽

E. Astrand

Keyword(s):

Image Processing ◽

High Speed ◽

Exposure Control ◽

Sensor Processing ◽

High Speed Image Processing

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The CC/IPP, an MIMD-SIMD architecture for image processing and pattern recognition

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97 ◽

10.1109/camp.1997.631887 ◽

2002 ◽

Cited By ~ 8

Author(s):

P. Jonker ◽

J. Vogelbruch

Keyword(s):

Image Processing ◽

Pattern Recognition ◽

Simd Architecture

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Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

An interactive tool for C.V. tutorials

A parallelizing method for implementing image processing tasks on SIMD linear processor arrays

A scalable architecture for low and intermediate level image processing

External loop unrolling of image processing programs: optimal register allocation for RISC architectures

Vision chip architecture using general-purpose processing elements for 1 ms vision system

Making a dataparallel language portable for massively parallel array computers

Asynchronous SIMD: an architectural concept for high performance image processing

Page segmentation using a pyramidal architecture

Analog sensor processing using exposure control. A new concept for high speed image processing

The CC/IPP, an MIMD-SIMD architecture for image processing and pattern recognition

Export Citation Format

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

An interactive tool for C.V. tutorials

A parallelizing method for implementing image processing tasks on SIMD linear processor arrays

A scalable architecture for low and intermediate level image processing

External loop unrolling of image processing programs: optimal register allocation for RISC architectures

Vision chip architecture using general-purpose processing elements for 1 ms vision system

Making a dataparallel language portable for massively parallel array computers

Asynchronous SIMD: an architectural concept for high performance image processing

Page segmentation using a pyramidal architecture

Analog sensor processing using exposure control. A new concept for high speed image processing

The CC/IPP, an MIMD-SIMD architecture for image processing and pattern recognition

Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97
Latest Publications