2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

2015 ◽

Cited By ~ 1

Author(s):

Hamid Mushtaq ◽

Zaid Al-Ars ◽

Koen Bertels

Keyword(s):

Execution Time ◽

Multicore Processors ◽

Worst Case ◽

Worst Case Execution Time

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Tejas: A java based versatile micro-architectural simulator

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347586 ◽

2015 ◽

Cited By ~ 21

Author(s):

Smruti R. Sarangi ◽

Rajshekar Kalayappan ◽

Prathmesh Kallurkar ◽

Seep Goel ◽

Eldhose Peter

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Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347595 ◽

2015 ◽

Cited By ~ 1

Author(s):

Mauricio Altieri ◽

Suzanne Lesecq ◽

Diego Puschini ◽

Olivier Heron ◽

Edith Beigne ◽

...

Keyword(s):

Temperature Sensor ◽

Aging Effects ◽

On Chip

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Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347603 ◽

2015 ◽

Cited By ~ 1

Author(s):

Sidinei Ghissoni ◽

Eduardo Costa ◽

Ricardo Reis

Keyword(s):

Power Efficient

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Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347587 ◽

2015 ◽

Cited By ~ 1

Author(s):

Soundous Chairat ◽

Edith Beigne ◽

Marc Belleville

Keyword(s):

Sensor Node ◽

Wireless Sensor ◽

Wireless Sensor Node ◽

Mixed Signal

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Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347583 ◽

2015 ◽

Author(s):

Anastasis Keliris ◽

Vasilis Dimitsas ◽

Olympia Kremmyda ◽

Dimitris Gizopoulos ◽

Michail Maniatakos

Keyword(s):

Wavelet Transform ◽

Discrete Wavelet Transform ◽

Discrete Wavelet ◽

Efficient Parallelization

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VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347589 ◽

2015 ◽

Cited By ~ 2

Author(s):

Nelson Alves Ferreira Neto ◽

Joaquim Ranyere S. de Oliveira ◽

Wagner Luiz A. de Oliveira ◽

Joao Carlos N. Bittencourt

Keyword(s):

Vlsi Architecture ◽

Architecture Design ◽

Design And Implementation ◽

Ieee 802.22

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Unified Power Format (UPF) methodology in a vendor independent flow

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347591 ◽

2015 ◽

Cited By ~ 3

Author(s):

Emilie Garat ◽

David Coriat ◽

Edith Beigne ◽

Leandro Stefanazzi

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Front matter

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347579 ◽

2015 ◽

Download Full-text

Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2015.7347601 ◽

2015 ◽

Cited By ~ 5

Author(s):

Lisa Durbeck ◽

Joseph G Tront ◽

Nicholas J Macias

Keyword(s):

Energy Efficiency ◽

Data Center ◽

Fabric Architecture

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2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Calculation of worst-case execution time for multicore processors using deterministic execution

Tejas: A java based versatile micro-architectural simulator

Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs

Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit

Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations

VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard

Unified Power Format (UPF) methodology in a vendor independent flow

Front matter

Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture

Export Citation Format

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Calculation of worst-case execution time for multicore processors using deterministic execution

Tejas: A java based versatile micro-architectural simulator

Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs

Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit

Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations

VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard

Unified Power Format (UPF) methodology in a vendor independent flow

Front matter

Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Latest Publications