The Sixth International Conference on VLSI Design
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Published By IEEE

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Preparing Engineers to meet the Challenges of the 21th Century through VLSI Education

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669659 ◽

2005 ◽

Author(s):

K. Prasad ◽

A. Goel

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Statistical Analysis of Controllability

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669638 ◽

2005 ◽

Cited By ~ 1

Author(s):

A. Majumdar ◽

S. Sastry

Keyword(s):

Statistical Analysis

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A Scheme For Synthesizing Testable Vlsi Designs With Minimum Area Overhead

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669657 ◽

2005 ◽

Author(s):

B. Mitra ◽

P.P. Chaudhuri

Keyword(s):

Minimum Area ◽

Area Overhead

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Efficient Technique to Reduce Gate Evaluations and Speed up Fault Simulation

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669650 ◽

2005 ◽

Author(s):

P.R.S. Kumar ◽

M.K. Srinivas ◽

J. Jacob

Keyword(s):

Fault Simulation ◽

Efficient Technique ◽

Speed Up

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State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669627 ◽

2005 ◽

Cited By ~ 3

Author(s):

R.A. Parekhji ◽

G. Venkatesh ◽

S.D. Sherlekar

Keyword(s):

Optimal Design ◽

Sequential Circuits ◽

State Assignment

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GB: A New Grid-Based Binding Approach for High-Level Synthesis

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669674 ◽

2005 ◽

Cited By ~ 1

Author(s):

Hyuk-Jae Jang ◽

B.M. Pangrle

Keyword(s):

High Level Synthesis ◽

High Level ◽

Grid Based

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NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669643 ◽

2005 ◽

Cited By ~ 5

Author(s):

R.K. Pal ◽

S.P. Pal ◽

A. Pal ◽

A.K. Dutta

Keyword(s):

Channel Routing ◽

Np Completeness

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Fault-Tolerant Arbitration in Multichip Crossbar Switches

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669709 ◽

2005 ◽

Cited By ~ 3

Author(s):

J. Ghosh ◽

N. Krishnamurthy

Keyword(s):

Fault Tolerant ◽

Crossbar Switches

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MHPS-Driven Early Design and Analysis of VLSI CPU Chips

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669691 ◽

2005 ◽

Cited By ~ 1

Author(s):

P. Bose ◽

J. Wellman

Keyword(s):

Early Design

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Delay Fault Test Generation with Cellular Aulhomata

The Sixth International Conference on VLSI Design ◽

10.1109/icvd.1993.669697 ◽

2005 ◽

Cited By ~ 3

Author(s):

S. Nandi ◽

B. Vamsi ◽

S. Chakraborty ◽

P.P. Chaudhuri ◽

S. Roy

Keyword(s):

Test Generation ◽

Delay Fault

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The Sixth International Conference on VLSI DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Preparing Engineers to meet the Challenges of the 21th Century through VLSI Education

Statistical Analysis of Controllability

A Scheme For Synthesizing Testable Vlsi Designs With Minimum Area Overhead

Efficient Technique to Reduce Gate Evaluations and Speed up Fault Simulation

State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits

GB: A New Grid-Based Binding Approach for High-Level Synthesis

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic

Fault-Tolerant Arbitration in Multichip Crossbar Switches

MHPS-Driven Early Design and Analysis of VLSI CPU Chips

Delay Fault Test Generation with Cellular Aulhomata

The Sixth International Conference on VLSI Design
Latest Publications