Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)
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Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766707 ◽

2005 ◽

Cited By ~ 3

Author(s):

S. Adham ◽

D. Burek ◽

C.J. Clark ◽

M. Collins ◽

G. Giles ◽

...

Keyword(s):

Scalable Architecture ◽

Embedded Cores

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P1500-CTL: Towards a Standard Core Test Language

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766708 ◽

2005 ◽

Cited By ~ 5

Author(s):

R. Kapur ◽

B. Keller ◽

B. Koenemann ◽

M. Lousberg ◽

P. Reuter ◽

...

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A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766648 ◽

2003 ◽

Cited By ~ 5

Author(s):

H. Takahashi ◽

K.O. Boateng ◽

Y. Takamatsu

Keyword(s):

New Method ◽

Single Fault

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Evaluating the fault tolerance capabilities of embedded systems via BDM

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766703 ◽

2003 ◽

Cited By ~ 11

Author(s):

M. Rebaudengo ◽

M. Sonza Reorda

Keyword(s):

Fault Tolerance ◽

Embedded Systems

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Test generation for ground bounce in internal logic circuitry

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766652 ◽

2003 ◽

Cited By ~ 6

Author(s):

Yi-Shing Chang ◽

S.K. Gupta ◽

M.A. Breuer

Keyword(s):

Test Generation ◽

Internal Logic ◽

Ground Bounce

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A novel test methodology for MEMS magnetic micromotors

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766677 ◽

2003 ◽

Cited By ~ 4

Author(s):

B.C. Kim ◽

K. Marella

Keyword(s):

Test Methodology

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Defect-oriented test scheduling

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766700 ◽

2003 ◽

Cited By ~ 21

Author(s):

Wanli Jiang ◽

B. Vinnakota

Keyword(s):

Test Scheduling

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Test metrics for analog parametric faults

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766670 ◽

2003 ◽

Cited By ~ 61

Author(s):

S. Sunter ◽

N. Nagi

Keyword(s):

Parametric Faults

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Enhanced BIST-based diagnosis of FPGAs via boundary scan access

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766697 ◽

2003 ◽

Cited By ~ 17

Author(s):

C. Hamilton ◽

G. Gibson ◽

S. Wijesuriya ◽

C. Stroud

Keyword(s):

Boundary Scan

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Simulation-based design error diagnosis and correction in combinational digital circuits

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766649 ◽

2003 ◽

Cited By ~ 10

Author(s):

D. Nayak ◽

D.M.H. Walker

Keyword(s):

Digital Circuits ◽

Error Diagnosis ◽

Design Error ◽

Simulation Based Design ◽

Simulation Based

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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores

P1500-CTL: Towards a Standard Core Test Language

A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations

Evaluating the fault tolerance capabilities of embedded systems via BDM

Test generation for ground bounce in internal logic circuitry

A novel test methodology for MEMS magnetic micromotors

Defect-oriented test scheduling

Test metrics for analog parametric faults

Enhanced BIST-based diagnosis of FPGAs via boundary scan access

Simulation-based design error diagnosis and correction in combinational digital circuits

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)
Latest Publications