Most of the research work to test the fast processors is carried out using external devices as testers;but it was not technically & financially workable. To fulfill the required performance along with providing efficient functionality, an appropriate testingism must be employed by the digital circuits. The best way is to follow testing as an integral part that is self-test. Conventionally large amount of data was stored in an external tester.But there was a difficulty in at speed testing performance using these external hardware. Hence, Builtin-self-test was invented which verifies failure free nature of circuit under test (CUT) with a test mechanism as a part of system itself. It is observed that, if testing of any hardware is carried out with the help of built-in self test, it increases the requirement of additional area and indirectly responsible for forfeits due to degradation in performance.. If a powerful and power optimized core is to be designed, hardware BIST cannot be afforded due to these limitations. To overcome these disadvantages, a new software based BIST techniques is introduced which relies on software test patterns. Here this paper focuses on rooting of software test routines which works using optimization of scheduling and also a Q- factor is proposed to evaluate the nature of proposed method.
Optimization of Scheduling Technique Rooted on Software Test Routines for Embedded Cores using Quality Factor