Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.

The Implementation of Genetic Algorithm in The Vehicle KIR Test Scheduling System

Based on the results of observations and data collection, the vehicle parking test services at the Salatiga City Transportation Agency have not implemented a structured scheduling system in managing their service schedules. This has resulted in an accumulation of the number of vehicles that exceed the service capacity on a working day. Therefore, a scheduling system is needed to assist the agency in arranging the due time schedule for the KIR test of a vehicle, and helping the vehicle owner community to find out the due time for the next KIR test. The scheduling method used is a genetic algorithm that is applied to a web-based application. The application is built using the PHP language and MySql database. With this website-based scheduling system application, it has made it easier for service officers to manage the KIR test service schedule, especially if there is a change in the number of vehicles.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.