International Workshop on System Level Interconnect Prediction
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9781457712418, 9781457712401, 9781457712395

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International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135438 ◽

2011 ◽

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A SAT-based routing algorithm for cross-referencing biochips

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135436 ◽

2011 ◽

Cited By ~ 4

Author(s):

Ping-Hung Yuh ◽

Cliff Chiung-Yu Lin ◽

Tsung-Wei Huang ◽

Tsung-Yi Ho ◽

Chia-Lin Yang ◽

...

Keyword(s):

Routing Algorithm

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Distributed power network co-design with on-chip power supplies and decoupling capacitors

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135434 ◽

2011 ◽

Cited By ~ 14

Author(s):

Selcuk Kose ◽

Eby G. Friedman

Keyword(s):

Power Supplies ◽

Power Network ◽

Decoupling Capacitors ◽

Distributed Power ◽

On Chip

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Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135435 ◽

2011 ◽

Cited By ~ 16

Author(s):

Dae Hyun Kim ◽

Suyoun Kim ◽

Sung Kyu Lim

Keyword(s):

3D Ic ◽

Through Silicon Vias ◽

Nano Scale ◽

Silicon Vias

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Mobile system considerations for SDRAM interface trends

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135437 ◽

2011 ◽

Cited By ~ 8

Author(s):

Andrew B. Kahng ◽

Vaishnav Srinivas

Keyword(s):

Mobile System

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Performance and power analysis of through silicon via based 3D IC integration

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135439 ◽

2011 ◽

Cited By ~ 3

Author(s):

Hung Viet Nguyen ◽

Myunghwan Ryu ◽

Youngmin Kim

Keyword(s):

Power Analysis ◽

3D Ic ◽

Through Silicon Via

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System interconnect design exploration for embedded MPSoCs

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135433 ◽

2011 ◽

Author(s):

Chen-Ling Chou ◽

Radu Marculescu ◽

Umit Ogras ◽

Satrajit Chatterjee ◽

Michael Kishinevsky ◽

...

Keyword(s):

Design Exploration ◽

Interconnect Design

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Interface optimization for improved routability in chip-package-board co-design

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135430 ◽

2011 ◽

Cited By ~ 4

Author(s):

Tilo Meister ◽

Jens Lienig ◽

Gisbert Thomke

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Reducing energy and increasing performance with traffic optimization in many-core systems

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135429 ◽

2011 ◽

Cited By ~ 1

Author(s):

George B. P. Bezerra ◽

Stephanie Forrest ◽

Payman Zarkesh-Ha

Keyword(s):

Many Core ◽

Traffic Optimization ◽

Reducing Energy

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Wirelength and congestion estimation for routability-driven placement

International Workshop on System Level Interconnect Prediction ◽

10.1109/slip.2011.6135441 ◽

2011 ◽

Cited By ~ 1

Author(s):

Yang Yang Li ◽

Logan Rakai ◽

Laleh Behjat ◽

Bill Swartz

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International Workshop on System Level Interconnect PredictionLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Table of content

A SAT-based routing algorithm for cross-referencing biochips

Distributed power network co-design with on-chip power supplies and decoupling capacitors

Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs

Mobile system considerations for SDRAM interface trends

Performance and power analysis of through silicon via based 3D IC integration

System interconnect design exploration for embedded MPSoCs

Interface optimization for improved routability in chip-package-board co-design

Reducing energy and increasing performance with traffic optimization in many-core systems

Wirelength and congestion estimation for routability-driven placement

International Workshop on System Level Interconnect Prediction
Latest Publications