Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias

An accurate equivalent thermal model is proposed to calculate the equivalent thermal conductivity (ETC) of shield differential through-silicon via (SDTSV). The mathematical expressions of ETC in both horizontal and vertical directions are deduced by considering the anisotropy of SDTSV. The accuracy of the proposed model is verified by the finite element method (FEM), and the average errors of temperature along the X-axis, Y-axis, diagonal line, and vertical directions are 1.37%, 3.42%, 1.76%, and 0.40%, respectively. Compared with COMSOL, the proposed model greatly improves the computational efficiency. Moreover, the effects of different parameters on the thermal distribution of SDTSV are also investigated. The thermal conductivity is decreased with the increase in thickness of SiO2. With the increase in pitch, the maximum temperature of SDTSV increases very slowly when β = 0°, and decreases very slowly when β = 90°. The proposed model can be used to accurately and quickly describe the thermal distribution of SDTSV, which has a great prospect in the design of 3D IC.