17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781479945580, 9781479945603

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Timing-aware ATPG for critical paths with multiple TSVs

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868774 ◽

2014 ◽

Author(s):

C. Metzler ◽

A. Todri-Sanial ◽

A. Bosio ◽

L. Dilillo ◽

P. Girard ◽

...

Keyword(s):

Critical Paths

Download Full-text

Foreword to the 17th IEEE DDECS symposium

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868748 ◽

2014 ◽

Download Full-text

On NFA-split architecture optimizations

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868808 ◽

2014 ◽

Author(s):

Vlastimil Kosar ◽

Jan Korenek

Keyword(s):

Split Architecture

Download Full-text

Symposium committees

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868749 ◽

2014 ◽

Download Full-text

FPGA design of the computation unit for the semi-global stereo matching algorithm

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868796 ◽

2014 ◽

Cited By ~ 8

Author(s):

Mikolaj Roszkowski ◽

Grzegorz Pastuszak

Keyword(s):

Stereo Matching ◽

Fpga Design ◽

Matching Algorithm

Download Full-text

Lower bounds of the size of Shared Structurally Synthesized BDDs

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868767 ◽

2014 ◽

Cited By ~ 1

Author(s):

Raimund Ubar ◽

Dmitri Mironov

Keyword(s):

Lower Bounds

Download Full-text

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868750 ◽

2014 ◽

Download Full-text

Automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868752 ◽

2014 ◽

Cited By ~ 1

Author(s):

Lech Jozwiak

Keyword(s):

Cyber Physical Systems ◽

Massively Parallel ◽

Physical Systems ◽

Architecture Exploration

Download Full-text

Emulation based fault injection on UHF RFID transponder

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868802 ◽

2014 ◽

Author(s):

Omar Abdelmalek ◽

David Hely ◽

Vincent Beroulle

Keyword(s):

Fault Injection ◽

Uhf Rfid

Download Full-text

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2014.6868768 ◽

2014 ◽

Cited By ~ 1

Author(s):

Roel Jordans ◽

Erkan Diken ◽

Lech Jozwiak ◽

Henk Corporaal

Keyword(s):

Architecture Exploration

Download Full-text

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Timing-aware ATPG for critical paths with multiple TSVs

Foreword to the 17th IEEE DDECS symposium

On NFA-split architecture optimizations

Symposium committees

FPGA design of the computation unit for the semi-global stereo matching algorithm

Lower bounds of the size of Shared Structurally Synthesized BDDs

Table of contents

Automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems

Emulation based fault injection on UHF RFID transponder

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

Export Citation Format

17th International Symposium on Design and Diagnostics of Electronic Circuits & SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Timing-aware ATPG for critical paths with multiple TSVs

Foreword to the 17th IEEE DDECS symposium

On NFA-split architecture optimizations

Symposium committees

FPGA design of the computation unit for the semi-global stereo matching algorithm

Lower bounds of the size of Shared Structurally Synthesized BDDs

Table of contents

Automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems

Emulation based fault injection on UHF RFID transponder

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
Latest Publications