2006 IEEE International High Level Design Validation and Test Workshop
Latest Publications

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Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Semi-Formal Verification at IBM

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319981 ◽

2006 ◽

Cited By ~ 1

Author(s):

Jason Baumgartner

Keyword(s):

Formal Verification

Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.320005 ◽

2006 ◽

Cited By ~ 6

Author(s):

Hsiou-wen Hsueh ◽

Kerstin Eder

Keyword(s):

Logic Programming ◽

Inductive Logic Programming ◽

Inductive Logic ◽

Functional Coverage

Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319984 ◽

2006 ◽

Cited By ~ 2

Author(s):

Tasuku Nishihara ◽

Takeshi Matsumoto ◽

Masahiro Fujita

Keyword(s):

High Level Synthesis ◽

Equivalence Checking ◽

Rule Based ◽

High Level

Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319985 ◽

2006 ◽

Cited By ~ 1

Author(s):

In-ho Moon ◽

Per Bjesse ◽

Carl Pixley

Keyword(s):

Equivalence Checking ◽

Don't Cares ◽

Sequential Equivalence Checking

Panel: Assertion-Based Verification -What's the Big Deal?

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319989 ◽

2006 ◽

Cited By ~ 3

Author(s):

Sandeep Shukla ◽

Alan Hu ◽

Jacob Abrahams ◽

Pranav Ashar ◽

Harry Foster ◽

...

DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319971 ◽

2006 ◽

Cited By ~ 4

Author(s):

Allon Adir ◽

Laurent Fournier ◽

Yoav Katz ◽

Anatoly Koyfman

Keyword(s):

Functional Verification ◽

Model Based ◽

Address Translation

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319966 ◽

2006 ◽

Cited By ~ 29

Author(s):

Marc Boule ◽

Zeljko Zilic

MMV: Metamodeling Based Microprocessor Valiation Environment

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319978 ◽

2006 ◽

Cited By ~ 2

Author(s):

Ajit Dingankar ◽

Deepak Mathaikutty ◽

Sreekumar Kodakara ◽

Sandeep Shukla ◽

David Lilja

Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319997 ◽

2006 ◽

Cited By ~ 1

Author(s):

Stergios Stergiou ◽

Jawahar Jain

Keyword(s):

Reachability Analysis ◽

Transition Relation

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

2006 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2006.319996 ◽

2006 ◽

Cited By ~ 18

Author(s):

Amer Samarah ◽

Ali Habibi ◽

Sofiene Tahar ◽

Nawwaf Kharma

Keyword(s):

Genetic Algorithm ◽

Test Generation ◽

A Cell

2006 IEEE International High Level Design Validation and Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Semi-Formal Verification at IBM

Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis

Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces

Panel: Assertion-Based Verification -What's the Big Deal?

DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

MMV: Metamodeling Based Microprocessor Valiation Environment

Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

2006 IEEE International High Level Design Validation and Test Workshop
Latest Publications