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Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
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TOTAL DOCUMENTS
8
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1
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Published By ACM Press
9781450339636
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Latest Documents
Most Cited Documents
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System-Level Analysis of Network Interfaces for Hierarchical MPSoCs
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
◽
10.1145/2835512.2835513
◽
2015
◽
Cited By ~ 4
Author(s):
Johannes Ax
◽
Gregor Sievers
◽
Martin Flasskamp
◽
Wayne Kelly
◽
Thorsten Jungeblut
◽
...
Keyword(s):
System Level
◽
Network Interfaces
◽
Level Analysis
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NoCVision
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
◽
10.1145/2835512.2835518
◽
2015
◽
Author(s):
Vaibhav Gogte
◽
Doowon Lee
◽
Ritesh Parikh
◽
Valeria Bertacco
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Task mapping and communication routing model for minimizing power consumption in multi-cores
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
◽
10.1145/2835512.2835515
◽
2015
◽
Cited By ~ 1
Author(s):
Sergiu Carpov
Keyword(s):
Power Consumption
◽
Task Mapping
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Automated Power and Latency Management in Heterogeneous 3D NoCs
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
◽
10.1145/2835512.2835517
◽
2015
◽
Author(s):
Awet Yemane WeldeZion
◽
Masoumeh Ebrahimi
◽
Masoud Daneshtalab
◽
Hannu Tenhunen
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A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
◽
10.1145/2835512.2835519
◽
2015
◽
Author(s):
Jian Jie
◽
Lai Mingche
◽
Xiao Liquan
Keyword(s):
Quality Of Service
◽
High Throughput
◽
Low Latency
◽
Multiple Level
◽
On Chip
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Methodology to verify, debug and evaluate performances of NoC based interconnects
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
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10.1145/2835512.2835521
◽
2015
◽
Author(s):
Patrick Oury
◽
Nick Heaton
◽
Stewart Penman
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Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
◽
10.1145/2835512.2835514
◽
2015
◽
Author(s):
Poona Bahrebar
◽
Dirk Stroobandt
Keyword(s):
Cost Effective
◽
Networks On Chip
◽
On Chip
◽
3D Networks
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Rethinking Memory System Design (along with Interconnects)
Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
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10.1145/2835512.2835520
◽
2015
◽
Author(s):
Onur Mutlu
Keyword(s):
System Design
◽
Memory System
◽
Memory System Design
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