Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Latest Publications

TOTAL DOCUMENTS

307

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Published By Research Publishing Services

9783981537079

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Topaz: Mining High-Level Safety Properties from Logic Simulation Traces

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0529 ◽

2016 ◽

Cited By ~ 1

Author(s):

Ahmed Nassar ◽

Fadi J. Kurdahi ◽

Salam R. Zantout

Keyword(s):

Safety Properties ◽

Logic Simulation ◽

High Level

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Lossless Compression Algorithm Based on Dictionary Coding for Multiple E-Beam Direct Write System

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0515 ◽

2016 ◽

Cited By ~ 1

Author(s):

Pei-Chun Lin ◽

Yu-Hsuan Pai ◽

Yu-Hsiang Chiu ◽

Shao-Yuan Fang ◽

Charlie Chung-Ping Chen

Keyword(s):

Lossless Compression ◽

Compression Algorithm ◽

Direct Write

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Buffered Compares: Excavating the Hidden Parallelism Inside DRAM Architectures with Lightweight Logic

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0512 ◽

2016 ◽

Cited By ~ 1

Author(s):

Jinho Lee ◽

Jung Ho Ahn ◽

Kiyoung Choi

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A Fast Manufacturability Aware Optical Proximity Correction (OPC) Algorithm with Adaptive Wafer Image Estimation

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0509 ◽

2016 ◽

Cited By ~ 1

Author(s):

Ahmed Awad ◽

Atsushi Takahashi ◽

Chikaaki Kodama

Keyword(s):

Image Estimation ◽

Optical Proximity Correction

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PhoNoCMap: an Application Mapping Tool for Photonic Networks-on-Chip

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0283 ◽

2016 ◽

Cited By ~ 4

Author(s):

Edoardo Fusella ◽

Alessandro Cilardo

Keyword(s):

Photonic Networks ◽

Networks On Chip ◽

Application Mapping ◽

Mapping Tool ◽

On Chip

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Captopril: Reducing the Pressure of Bit Flips on Hot Locations in Non-Volatile Main Memories

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0032 ◽

2016 ◽

Cited By ~ 1

Author(s):

Majid Jalili ◽

Hamid Sarbazi-Azad

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PAIS: Parallelization Aware Instruction Scheduling for Improving Soft-error Reliability of GPU-based Systems

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0869 ◽

2016 ◽

Cited By ~ 1

Author(s):

Haeseung Lee ◽

Hsinchung Chen ◽

Mohammad Abdullah Al Faruque

Keyword(s):

Instruction Scheduling ◽

Soft Error

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Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0833 ◽

2016 ◽

Cited By ~ 10

Author(s):

Atul Rahman ◽

Jongeun Lee ◽

Kiyoung Choi

Keyword(s):

Neural Networks ◽

Convolutional Neural Networks ◽

Fpga Acceleration

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Efficient Program Tracing and Monitoring Through Power Consumption — With a Little Help from the Compiler

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0829 ◽

2016 ◽

Cited By ~ 2

Author(s):

Carlos Moreno ◽

Sean Kauffman ◽

Sebastian Fischmeister

Keyword(s):

Power Consumption ◽

Efficient Program

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Automated Test Generation for Debugging Arithmetic Circuits

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0823 ◽

2016 ◽

Cited By ~ 7

Author(s):

Farimah Farahmandi ◽

Prabhat Mishra

Keyword(s):

Test Generation ◽

Arithmetic Circuits ◽

Automated Test Generation ◽

Automated Test

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Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Research Publishing Services

Topaz: Mining High-Level Safety Properties from Logic Simulation Traces

Lossless Compression Algorithm Based on Dictionary Coding for Multiple E-Beam Direct Write System

Buffered Compares: Excavating the Hidden Parallelism Inside DRAM Architectures with Lightweight Logic

A Fast Manufacturability Aware Optical Proximity Correction (OPC) Algorithm with Adaptive Wafer Image Estimation

PhoNoCMap: an Application Mapping Tool for Photonic Networks-on-Chip

Captopril: Reducing the Pressure of Bit Flips on Hot Locations in Non-Volatile Main Memories

PAIS: Parallelization Aware Instruction Scheduling for Improving Soft-error Reliability of GPU-based Systems

Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array

Efficient Program Tracing and Monitoring Through Power Consumption — With a Little Help from the Compiler

Automated Test Generation for Debugging Arithmetic Circuits

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Latest Publications