A dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection
2008 ◽
Vol 128
(7)
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pp. 1185-1190
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1992 ◽
Vol 50
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pp. 1262-1263
2015 ◽
Vol 03
(02)
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pp. 651-658
2015 ◽
Vol 03
(07)
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pp. 6801-6807
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Keyword(s):
2015 ◽
Vol 03
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pp. 5012-5023
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2014 ◽
Vol 9
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pp. 1621
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2014 ◽
Vol 9
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pp. 1060
2014 ◽
Vol E97.A
(11)
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pp. 2130-2138