Hardware/Software Codesign of Reconfigurable Architectures Using UML

UML for SOC Design ◽

10.1007/0-387-25745-4_5 ◽

2006 ◽

pp. 89-117 ◽

Cited By ~ 1

Author(s):

Bernd Steinbach ◽

Dominik Fröhlich ◽

Thomas Beierlein

Keyword(s):

Reconfigurable Architectures

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Reconvering faulty Non-volatile Flip Flops for Coarse-Grained Reconfigurable Architectures

IEICE Transactions on Electronics ◽

10.1587/transele.2020lhp0002 ◽

2020 ◽

Author(s):

Takeharu IKEZOE ◽

Takuya KOJIMA ◽

Hideharu AMANO

Keyword(s):

Coarse Grained ◽

Reconfigurable Architectures

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Exploring the acceleration of Nekbone on reconfigurable architectures

2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) ◽

10.1109/h2rc51942.2020.00008 ◽

2020 ◽

Author(s):

Nick Brown

Keyword(s):

Reconfigurable Architectures

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High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2161217 ◽

2011 ◽

Vol 30 (11) ◽

pp. 1599-1609 ◽

Cited By ~ 22

Author(s):

Yongjoo Kim ◽

Jongeun Lee ◽

A. Shrivastava ◽

J. W. Yoon ◽

Doosan Cho ◽

...

Keyword(s):

High Throughput ◽

Coarse Grained ◽

Reconfigurable Architectures ◽

Data Mapping ◽

High Throughput Data

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Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures

2011 International Conference on Reconfigurable Computing and FPGAs ◽

10.1109/reconfig.2011.57 ◽

2011 ◽

Cited By ~ 12

Author(s):

Thomas Schweizer ◽

Philipp Schlicker ◽

Sven Eisenhardt ◽

Tommy Kuhn ◽

Wolfgang Rosenstiel

Keyword(s):

Fault Tolerance ◽

Low Cost ◽

Coarse Grained ◽

Reconfigurable Architectures

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System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures

Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03 ◽

10.1145/951710.951722 ◽

2003 ◽

Cited By ~ 16

Author(s):

Juanjo Noguera ◽

Rosa M. Badia

Keyword(s):

Task Scheduling ◽

System Level ◽

Reconfigurable Architectures ◽

Power Performance ◽

Dynamically Reconfigurable ◽

Trade Offs

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HERA: Hardware evolution over reconfigurable architectures

2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE) ◽

10.1109/change.2011.6172448 ◽

2011 ◽

Cited By ~ 6

Author(s):

Davide Basilio Bartolini ◽

Fabio Cancare ◽

Matteo Carminati ◽

Donatella Sciuto

Keyword(s):

Reconfigurable Architectures

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A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers

IEEE Communications Magazine ◽

10.1109/mcom.2003.1166666 ◽

2003 ◽

Vol 41 (1) ◽

pp. 105-113 ◽

Cited By ~ 26

Author(s):

R. Baines ◽

D. Pulley

Keyword(s):

Reconfigurable Architectures ◽

Wireless Receivers ◽

Total Cost ◽

Cost Approach ◽

Baseband Processing

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Shared reconfigurable architectures for CMPS

2008 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2008.4629948 ◽

2008 ◽

Cited By ~ 7

Author(s):

Matthew A. Watkins ◽

Mark J. Cianchetti ◽

David H. Albonesi

Keyword(s):

Reconfigurable Architectures

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Session MA5: Programmable and reconfigurable architectures

2008 42nd Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2008.5074381 ◽

2008 ◽

Author(s):

Suleyman Demirsoy

Keyword(s):

Reconfigurable Architectures

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Reconfigurable architectures for mesh-arrays with PE and link faults

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI ◽

10.1109/dftvs.1995.476943 ◽

2002 ◽

Cited By ~ 1

Author(s):

I. Takanami ◽

T. Horita

Keyword(s):

Reconfigurable Architectures

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