A Symbolic Model Checker for tccp Programs

2005 ◽  
pp. 45-56
Author(s):  
M. Alpuente ◽  
M. Falaschi ◽  
A. Villanueva
Keyword(s):  
Model Checker ◽  
Symbolic Model

VERIFICATION OF DATAFLOW SCHEDULING

2008 ◽  
Vol 18 (06) ◽  
pp. 737-758
Author(s):  
TSUNG-HSI CHIANG ◽  
LAN-RONG DUNG
Keyword(s):  
Formal Verification ◽  
Petri Net ◽  
Register Transfer Level ◽  
Functional Verification ◽  
Model Checker ◽  
Symbolic Model ◽  
Verification Method ◽  
Level Design ◽  
High Level ◽  
Design Scheduling

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

SMC4AC: A New Symbolic Model Checker for Intelligent Agent Communication

2017 ◽  
Vol 152 (3) ◽  
pp. 223-271 ◽  
Author(s):  
Warda El Kholy ◽  
Jamal Bentahar ◽  
Mohamed El Menshawy ◽  
Hongyang Qu ◽  
Rachida Dssouli
Keyword(s):  
Intelligent Agent ◽  
Model Checker ◽  
Symbolic Model ◽  
Agent Communication

VERIFYING VERY LARGE INDUSTRIAL CIRCUITS USING 100 PROCESSES AND BEYOND

2007 ◽  
Vol 18 (01) ◽  
pp. 45-61 ◽  
Author(s):  
LIMOR FIX ◽  
ORNA GRUMBERG ◽  
AMNON HEYMAN ◽  
TAMIR HEYMAN ◽  
ASSAF SCHUSTER
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Real Life ◽  
Distributed Model ◽  
Computational Grids ◽  
Great Promise ◽  
Model Checker ◽  
Symbolic Model ◽  
Computing Platforms ◽  
Industrial Circuits

Recent advances in scheduling and networking have paved the way for efficient exploitation of large-scale distributed computing platforms such as computational grids and huge clusters. Such infrastructures hold great promise for the highly resource-demanding task of verifying and checking large models, given that model checkers would be designed with a high degree of scalability and flexibility in mind. In this paper we focus on the mechanisms required to execute a high-performance, distributed, symbolic model checker on top of a large-scale distributed environment. We develop a hybrid algorithm for slicing the state space and dynamically distribute the work among the worker processes. We show that the new approach is faster, more effective, and thus much more scalable than previous slicing algorithms. We then present a checkpoint-restart module that has very low overhead. This module can be used to combat failures, the likelihood of which increases with the size of the computing plat-form. However, checkpoint-restart is even more handy for the scheduling system: it can be used to avoid reserving large numbers of workers, thus making the distributed computation work-efficient. Finally, we discuss for the first time the effect of reorder on the distributed model checker and show how the distributed system performs more efficient reordering than the sequential one. We implemented our contributions on a network of 200 processors, using a distributed scalable scheme that employs a high-performance industrial model checker from Intel. Our results show that the system was able to verify real-life models much larger than was previously possible.

scholarly journals Bounded Model Checking of ETL Cooperating with Finite and Looping Automata Connectives

2013 ◽  
Vol 2013 ◽  
pp. 1-12 ◽  
Author(s):  
Rui Wang ◽  
Wanwei Liu ◽  
Tun Li ◽  
Xiaoguang Mao ◽  
Ji Wang
Keyword(s):  
Model Checking ◽  
Temporal Logic ◽  
Bounded Model Checking ◽  
Symbolic Model Checking ◽  
Model Checker ◽  
Symbolic Model ◽  
Complementary Technique

As a complementary technique of the BDD-based approach, bounded model checking (BMC) has been successfully applied to LTL symbolic model checking. However, the expressiveness of LTL is rather limited, and some important properties cannot be captured by such logic. In this paper, we present a semantic BMC encoding approach to deal with the mixture ofETLfandETLl. Since such kind of temporal logic involves both finite and looping automata as connectives, all regular properties can be succinctly specified with it. The presented algorithm is integrated into the model checker ENuSMV, and the approach is evaluated via conducting a series of imperial experiments.

dmcG: A Distributed Symbolic Model Checker Based on GreatSPN

2007 ◽  
pp. 495-504 ◽  
Author(s):  
Alexandre Hamez ◽  
Fabrice Kordon ◽  
Yann Thierry-Mieg ◽  
Fabrice Legond-Aubry
Keyword(s):  
Model Checker ◽  
Symbolic Model
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