Formal Development of Mechanisms for Tolerating Transient Faults

2006 ◽  
pp. 189-209 ◽  
Author(s):  
Dubravka Ilić ◽  
Elena Troubitsyna ◽  
Linas Laibinis ◽  
Colin Snook
Keyword(s):  
Transient Faults ◽  
Formal Development

The Rhythms of Reiteration: Formal Development in Stravinsky's Ostinati

1992 ◽  
Vol 14 (2) ◽  
pp. 171-187 ◽  
Author(s):  
Gretchen Horlacher
Keyword(s):  
Formal Development

Pilot Tests of FasTR Method for Locating Transient Faults in Medium Voltage Underground Power Networks

2020 ◽  
pp. 1-1
Author(s):  
Moussa Kafal ◽  
Nicolas Gregis ◽  
Jaume Benoit ◽  
Nicolas Ravot ◽  
Clara Lagomarsini ◽  
...  
Keyword(s):  
Transient Faults ◽  
Power Networks ◽  
Medium Voltage ◽  
Pilot Tests

Precise Cache Profiling for Studying Radiation Effects

2021 ◽  
Vol 20 (3) ◽  
pp. 1-25
Author(s):  
James Marshall ◽  
Robert Gifford ◽  
Gedare Bloom ◽  
Gabriel Parmer ◽  
Rahul Simha
Keyword(s):  
Radiation Effects ◽  
Fault Injection ◽  
Error Correcting Codes ◽  
Direct Access ◽  
Transient Faults ◽  
Large Area ◽  
Common Multiple ◽  
Single Event Upsets ◽  
On Chip ◽  
Future Work

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

scholarly journals Toward formal development of programs from algebraic specifications: Parameterisation revisited

1992 ◽  
Vol 29 (8) ◽  
pp. 689-736 ◽  
Author(s):  
Donald Sannella ◽  
Stefan Sokolowski ◽  
Andrzej Tarlecki
Keyword(s):  
Algebraic Specifications ◽  
Formal Development
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