State-Burst Feedback Control for Fault Recovery of Input/State Asynchronous Sequential Machines

Static corrective controllers are more efficient than dynamic ones since they consist of only logic elements, whereas their existence conditions are more restrictive. In this paper, we present a static corrective control scheme for fault diagnosis and fault tolerant control of input/state asynchronous sequential machines (ASMs) vulnerable to transient faults. The design flexibility of static controllers is enlarged by virtue of using a diagnoser and state bursts. Necessary and sufficient conditions for the existence of a diagnoser and static fault tolerant controller are presented, and the process of controller synthesis is addressed based on the derived condition. Illustrative examples on practical ASMs are provided to show the applicability of the proposed scheme.

A Novel Island Detection Threshold Setting Using Phasor Measurement Unit Voltage Angle in a Distribution Network

Islanding detection needs are becoming a pivotal constituent of the power system, since the penetration of distributed generators in the utility power system is continually increasing. Accurate threshold setting is an integral part of the island detection scheme since an inappropriate threshold might cause a hazardous situation. This study looked at the islanding conditions as well as two transient faults, such as a single line to ground fault and a three-phase balance fault, to assess the event distinguishing ability of the proposed method. Therefore, the goal of this research was to determine the threshold of the island if the distributed generator (DG) capacity is greater than the connected feeder load, which is the over-frequency island condition, and if the DG capacity is less than the connected feeder load, which is the under-frequency island condition. The significance of this research work is to propose a new island detection threshold setting method using the slip angle and acceleration angle that comes from phasor measurement unit (PMU) voltage angle data. The proposed threshold setting method was simulated in the PowerWorld simulator on a modified IEEE 30 bus system equipped with DG. There are three different interconnection scenarios in the test system and the performance of the proposed method shows that getting the island threshold for all the scenarios requires a single time step or 20 mile seconds after incepting an island into the network. In addition, it can distinguish between the real islanding threshold and the transient faults threshold.

An SVM-Based NAND Flash Endurance Prediction Method

NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us.

Reliability-aware Scheduling and Routing for Messages in Time-sensitive Networking

Time-sensitive Networking (TSN) on Ethernet is a promising communication technology in the automotive and industrial automation industries due to its real-time and high-bandwidth communication capabilities. Time-triggered scheduling and static routing are often adopted in these areas due to high requirements on predictability for safety-critical applications. Deadline-constrained routing and scheduling in TSN have been studied extensively in past research. However, scheduling and routing with reliability requirements in the context of transient faults are not yet studied. In this work, we propose an Satisfiability Modulo Theory-based technique to perform scheduling and routing that takes both reliability constraints and end-to-end deadline constraints into consideration. Heuristics have been applied to improve the scalability of the solution. Extensive experiments have been conducted to demonstrate the efficiency of our proposed technique.

Precise Cache Profiling for Studying Radiation Effects

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.