scholarly journals Intelligent Systems Engineering with Reconfigurable Computing

2006 ◽  
pp. 161-170
Author(s):  
Iouliia Skliarova
Keyword(s):  
Systems Engineering ◽  
Reconfigurable Computing ◽  
Intelligent Systems

Frameworks for developing intelligent systems: The ABE systems engineering environment

IEEE Expert ◽  
1991 ◽  
Vol 6 (3) ◽  
pp. 30-40 ◽  
Author(s):  
F. Hayes-Roth ◽  
J.E. Davidson ◽  
L.D. Erman ◽  
J.S. Lark
Keyword(s):  
Systems Engineering ◽  
Intelligent Systems ◽  
Engineering Environment

Intelligent Systems Engineering

1993 ◽  
Vol 4 (2) ◽  
pp. 54
Author(s):  
Peter Smeaton
Keyword(s):  
Systems Engineering ◽  
Intelligent Systems

FPGA-Based Hardware Accelerator for an Embedded Factor Graph with Configurable Optimization

2018 ◽  
Vol 28 (02) ◽  
pp. 1950031 ◽  
Author(s):  
Indar Sugiarto ◽  
Cristian Axenie ◽  
Jörg Conradt
Keyword(s):  
Reconfigurable Computing ◽  
Intelligent Systems ◽  
Factor Graph ◽  
Optimized Design ◽  
Inference Process ◽  
Constrained System ◽  
Inference Mechanism ◽  
Model Combining ◽  
Hardware Resource ◽  
On Chip

A factor graph (FG) can be considered as a unified model combining a Bayesian network (BN) and a Markov random field (MRF). The inference mechanism of a FG can be used to perform reasoning under incompleteness and uncertainty, which is a challenging task in many intelligent systems and robotics. Unfortunately, a complete inference mechanism requires intense computations that introduces a long delay for the reasoning process to complete. Furthermore, in an energy-constrained system such as a mobile robot, it is required to have a very efficient inference process. In this paper, we present an embedded FG inference engine that employs a neural-inspired discretization mechanism. The engine runs on a system-on-chip (SoC) and is accelerated by its FPGA. We optimized our design to balance the trade-off between speed and hardware resource utilization. In our fully-optimized design, it can accelerate the inference process eight times faster than the normal execution, which is twice the speed-up gain achieved by a parallelized FG running on a PC. The experiments demonstrate that our design can be extended into an efficient reconfigurable computing machine.

scholarly journals Logic programming as a service

2018 ◽  
Vol 18 (5-6) ◽  
pp. 846-873 ◽  
Author(s):  
ROBERTA CALEGARI ◽  
ENRICO DENTI ◽  
STEFANO MARIANI ◽  
ANDREA OMICINI
Keyword(s):  
Distributed Systems ◽  
Logic Programming ◽  
Systems Engineering ◽  
Intelligent Systems ◽  
The Other ◽  
Service Oriented Architectures ◽  
Pervasive Systems ◽  
Architectural Model ◽  
Service Oriented ◽  
The One

AbstractNew generations of distributed systems are opening novel perspectives for logic programming (LP): On the one hand, service-oriented architectures represent nowadays the standard approach for distributed systems engineering; on the other hand, pervasive systems mandate for situated intelligence. In this paper, we introduce the notion ofLogic Programming as a Service(LPaaS) as a means to address the needs of pervasive intelligent systems through logic engines exploited as a distributed service. First, we define the abstract architectural model by re-interpreting classical LP notions in the new context; then we elaborate on the nature of LP interpreted as a service by describing the basic LPaaS interface. Finally, we show how LPaaS works in practice by discussing its implementation in terms of distributed tuProlog engines, accounting for basic issues such as interoperability and configurability.

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