Logic Level Power Estimation

2002 ◽  
pp. 169-201
Author(s):  
George Theodoridis ◽  
Costas Goutis
Keyword(s):  
Power Estimation ◽  
Logic Level

scholarly journals A Fast and Accurate Method of Power Estimation for Logic Level Networks

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 205-219
Author(s):  
G. Theodoridis ◽  
S. Theoharis ◽  
D. Soudris ◽  
C. Goutis
Keyword(s):  
Power Consumption ◽  
Power Estimation ◽  
Accurate Method ◽  
Experimental Results ◽  
Time Interval ◽  
Switching Activity ◽  
Data Correlations ◽  
Reduced Time ◽  
Logic Level

A method for estimating the power consumption of multilevel combinational networks is introduced. The proposed method has as inputs the signal probabilities, the data correlations of the primary inputs and the structure of the circuit, and consists of two major steps: (i) the calculation of the switching activity on an individual gate and (ii) the calculation of the switching activity of any node of the network. The foregoing step includes the derivation of novel formulas for calculating the switching activity of basic gates. The latter step includes the development of an algorithm, which propagates the signal probabilities through the network and calculates the switching activity of any logic node. The proposed method provides accurate switching activity values performing their calculation in reduced time interval. The experimental results prove that the proposed method achieves significant reduction up to 50% in terms of multiplications compared to method of [6].

POWER ESTIMATION AND OPTIMIZATION AT THE LOGIC LEVEL

1994 ◽  
Vol 05 (02) ◽  
pp. 179-202 ◽  
Author(s):  
MASSOUD PEDRAM
Keyword(s):  
Low Power ◽  
Power Analysis ◽  
Power Estimation ◽  
Technology Mapping ◽  
Symbolic Simulation ◽  
State Assignment ◽  
Simulation Techniques ◽  
Logic Level

This paper describes various approaches for power analysis and minimization at the logic level including, amongst others, pattern-independent probabilistic and symbolic simulation techniques for power estimation and low-power techniques for state assignment, logic restructuring, logic decomposition, technology mapping and pin ordering.

An Accurate and Efficient RTL Power Estimation based on Power Contour Model

2011 ◽  
Vol 131 (11) ◽  
pp. 1907-1914
Author(s):  
Hirofumi Kawauchi ◽  
Ittetsu Taniguchi ◽  
Hiroyuki Tomiyama ◽  
Masahiro Fukui
Keyword(s):  
Power Estimation ◽  
Contour Model
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