Simulation-Based Power Estimation of Low Power MD5 Design Techniques

2016 ◽  
Vol 2 (09) ◽  
pp. 625-630
Author(s):  
Shamsiah Binti Suhaili ◽  
Takahiro Watanabe
Author(s):  
Mangal Deep Gupta ◽  
‪Rajeev Kumar Chauhan

This paper presents a design of a binary comparator circuit using minimum fan-in logic gates (NAND-NOR) for achieving low power-delay-product (PDP). A 2-bit binary comparator circuit is re-designed to minimize fan-in of logic gates. Utilizing the concept of 2–bit comparator, a general gate-level architecture of a comparator system is proposed for higher input operands. A back-tracking model has been proposed in this work to estimate the worst-case performance in terms of delay and power or PDP for binary comparator circuits. It combines the advantages of the simulation-based method for power estimation and dynamic timing analysis (DTA) techniques for timing analysis. This work has also been extended for 20, 16, 14, 10, and 7-nm FINFET technology. The comparator circuits are simulated on Pyxis schematic tool by Mentor Graphics.


SIMULATION ◽  
1999 ◽  
Vol 72 (5) ◽  
pp. 320-326 ◽  
Author(s):  
Rajakrishnan Radjassamy ◽  
Jo Dale Carothers

2021 ◽  
Author(s):  
Ajay Kumar Sahu ◽  
Rashmi Samanth ◽  
Tanya Mendez ◽  
Subramanya G. Nayak ◽  
K. Vishnumurthy Kedlaya

2014 ◽  
Vol 494-495 ◽  
pp. 1640-1646
Author(s):  
Yu Lan ◽  
Xin Lu ◽  
Ye Shen He ◽  
Yun Feng Li

In the micro-power wireless transmission of the electric system, positions among modes are relatively fixed, power business data is reported at specific time points, and time distribution presents great differences. Key technologies of IEEE802.15.4 MAC layer protocol is expounded, shortages of collision detection and CSMA/CA on power business support, etc. are discussed, self-adaptive low-power consumption CSMA/CA algorithm which is more suitable for business of the electric system are designed and improved, and the algorithm goes through simulation experiment against the business characteristics of micro-power wireless network of the electric system. The simulation result demonstrates the algorithm may be greatly adapted to changes of network traffic under a relatively fixed environment of network topology on the premise of low power consumption.


VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.


2018 ◽  
Vol 106 (4) ◽  
pp. 2237-2246 ◽  
Author(s):  
Gaurav Verma ◽  
Vijay Khare ◽  
Manish Kumar

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