scholarly journals Checking Deadlock-Freedom of Parametric Component-Based Systems

2019 ◽  
pp. 3-20 ◽  
Author(s):  
Marius Bozga ◽  
Radu Iosif ◽  
Joseph Sifakis
Keyword(s):  
Deadlock Freedom

General composition for high level Petri nets and its properties

2012 ◽  
Vol 2 (3) ◽  
Author(s):  
Ivan Peťko ◽  
Štefan Hudák
Keyword(s):  
Petri Nets ◽  
Compositional Analysis ◽  
Deadlock Freedom ◽  
High Level

AbstractComposition of High Level Petri Nets in terms of joining relevant places and/or transitions is considered in the paper. In case of place composition type safe and combined types composition is contemplated. The process of composition is proposed and analysed in three separate cases with respect to the general approaches with minimal composition interface in each case but an analogous extension of the interface follows immediately from the approach introduced. Properties of the composition mechanism are analysed, namely preserving of boundedness, liveness and deadlock freedom. Conditions for preserving of the desired properties are introduced. Usability of the compositional mechanism is analysed in the process of de/compositional analysis.

A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom

2016 ◽  
Vol 24 (12) ◽  
pp. 3424-3436 ◽  
Author(s):  
Xiaolu Wang ◽  
Huaxi Gu ◽  
Yintang Yang ◽  
Kun Wang ◽  
Qinfen Hao
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
Deadlock Freedom ◽  
Network Diameter ◽  
On Chip

scholarly journals Deadlock-freedom (and safety) of transactions in a distributed database

1986 ◽  
Vol 33 (2) ◽  
pp. 161-178
Author(s):  
Ouri Wolfson ◽  
Mihalis Yannakakis
Keyword(s):  
Distributed Database ◽  
Deadlock Freedom

Design of Crossbar Arbiters in Tree-Based Routing Switches for On-Chip Networks

2014 ◽  
Vol 556-562 ◽  
pp. 5609-5613
Author(s):  
Hsin Chou Chi ◽  
Hsi Che Tseng ◽  
Han Shien Weng
Keyword(s):  
High Performance ◽  
Network Size ◽  
Mesh Network ◽  
Great Flexibility ◽  
Chip Area ◽  
Deadlock Freedom ◽  
Routing Switches ◽  
Diverse Application ◽  
On Chip ◽  
Application Requirements

The mesh network is an important topology for on-chip networks since it provides great flexibility for the on-chip interconnection with diverse application requirements. We have proposed the tree-based routing architecture for on-chip networks called TRAIN, which achieves deadlock freedom and high-performance communication for on-chip networks. With TRAIN, a packet arriving in a switch can be adaptively routed to utilize a shortcut to reduce the distance to the destination switch efficiently. In this paper, we propose two arbitration schemes in a TRAIN switch and their arbiter designs: the sequential arbiter and the shortcut-first arbiter. The experimental results show that the shortcut-first arbiter achieves better performance than the sequential arbiter, while the former costs larger chip area. With the network size grows, the performance advantage is more pronounced for the shortcut-first arbiter.

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