High-capacity strictly non-blocking optical switches based on new dual principle

In this paper the new dual principle of designing high-capacity strictly non-blocking optical switches is presented for the first time. The new type of switches with decentralized control based on the dual principle has been developed for the first time too. In accordance with the scheme topology this type of switching system was called as the quasi-complete dual switch. It also is analysed the optical signals minimal transmission time that provide the non-blocking property of the new schemes. For the circuit and link complexity calculations the accurate analytical expressions are obtained for the first time. The numerical investigation shows that the proposed schemes significantly benefit in comparison with the well-known switches, for example, the crossbar and Clos schemes. The results of comparing of the dual switch and other types of self-routing switches throughput show an obvious advantage of the proposed scheme. It also is shown that the offered switch type can be considered as a perspective for high-capacity strictly non-blocking optical systems. Indeed, the strictly non-blocking property, the scalability, high throughput, and the decentralized control are the main advantages of offered switches.

Minimizing the layout area of 2-input look up tables

This work investigates the minimum layout area of multiplexers, a fundamental building block of Field-Programmable Gate Arrays (FPGAs). In particular, we investigate the minimum layout area of 4:1 multiplexers, which are the building blocks of 2-input Look-Up Tables (LUTs) and can be recursively used to build higher order LUTs and multiplexer-based routing switches. We observe that previous work routes all four data inputs of 4:1 multiplexers on a single metal layer resulting in a wiring-area-dominated layout. In this work, we explore the various transistor-level placement options for implementing the 4:1 multiplexers while routing multiplexer data inputs through multiple metal layers in order to reduce wiring area. Feasible placement options with their corresponding data input distributions are then routed using an automated maze router and the routing results are then further manually refined. Through this systematic approach, we identified three 4:1 multiplexer layouts that are smaller than the previously proposed layouts by 30% to 35%. In particular, two larger layouts of the three are only 33% to 45% larger than layout area predicted by the two widely used active area models from previous FPGA architectural studies, and the smallest of the three layouts is 1% to 11% larger than the layout area predicted by these models.

Minimizing the layout area of 2-input look up tables

This work investigates the minimum layout area of multiplexers, a fundamental building block of Field-Programmable Gate Arrays (FPGAs). In particular, we investigate the minimum layout area of 4:1 multiplexers, which are the building blocks of 2-input Look-Up Tables (LUTs) and can be recursively used to build higher order LUTs and multiplexer-based routing switches. We observe that previous work routes all four data inputs of 4:1 multiplexers on a single metal layer resulting in a wiring-area-dominated layout. In this work, we explore the various transistor-level placement options for implementing the 4:1 multiplexers while routing multiplexer data inputs through multiple metal layers in order to reduce wiring area. Feasible placement options with their corresponding data input distributions are then routed using an automated maze router and the routing results are then further manually refined. Through this systematic approach, we identified three 4:1 multiplexer layouts that are smaller than the previously proposed layouts by 30% to 35%. In particular, two larger layouts of the three are only 33% to 45% larger than layout area predicted by the two widely used active area models from previous FPGA architectural studies, and the smallest of the three layouts is 1% to 11% larger than the layout area predicted by these models.

Design of Crossbar Arbiters in Tree-Based Routing Switches for On-Chip Networks

The mesh network is an important topology for on-chip networks since it provides great flexibility for the on-chip interconnection with diverse application requirements. We have proposed the tree-based routing architecture for on-chip networks called TRAIN, which achieves deadlock freedom and high-performance communication for on-chip networks. With TRAIN, a packet arriving in a switch can be adaptively routed to utilize a shortcut to reduce the distance to the destination switch efficiently. In this paper, we propose two arbitration schemes in a TRAIN switch and their arbiter designs: the sequential arbiter and the shortcut-first arbiter. The experimental results show that the shortcut-first arbiter achieves better performance than the sequential arbiter, while the former costs larger chip area. With the network size grows, the performance advantage is more pronounced for the shortcut-first arbiter.