scholarly journals On Weisfeiler-Leman Invariance: Subgraph Counts and Related Graph Properties

2019 ◽  
pp. 111-125 ◽  
Author(s):  
Vikraman Arvind ◽  
Frank Fuhlbrück ◽  
Johannes Köbler ◽  
Oleg Verbitsky
Keyword(s):  
Graph Properties ◽  
Related Graph

scholarly journals On Weisfeiler-Leman invariance: Subgraph counts and related graph properties

2020 ◽  
Vol 113 ◽  
pp. 42-59
Author(s):  
V. Arvind ◽  
Frank Fuhlbrück ◽  
Johannes Köbler ◽  
Oleg Verbitsky
Keyword(s):  
Graph Properties ◽  
Related Graph

Fuzzy Labeling on Cycle Related Graph

2019 ◽  
Vol 7 (6) ◽  
pp. 1192-1194
Author(s):  
M.K. Pandurangan ◽  
T. Bharathi ◽  
S.Antony Vinoth
Keyword(s):  
Related Graph

Homology of the line graph and of related graph-valued functions

1991 ◽  
Vol 56 (4) ◽  
pp. 400-404 ◽  
Author(s):  
Erich Prisner
Keyword(s):  
Line Graph ◽  
Related Graph

You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-25
Author(s):  
Michael Canesche ◽  
Westerley Carvalho ◽  
Lucas Reis ◽  
Matheus Oliveira ◽  
Salles Magalhães ◽  
...  
Keyword(s):  
Execution Time ◽  
High Performance ◽  
Coarse Grained ◽  
Optimal Placement ◽  
Greedy Heuristics ◽  
High Quality ◽  
Solution Quality ◽  
Graph Traversal ◽  
Trade Offs ◽  
Graph Properties

Coarse-grained reconfigurable architecture (CGRA) mapping involves three main steps: placement, routing, and timing. The mapping is an NP-complete problem, and a common strategy is to decouple this process into its independent steps. This work focuses on the placement step, and its aim is to propose a technique that is both reasonably fast and leads to high-performance solutions. Furthermore, a near-optimal placement simplifies the following routing and timing steps. Exact solutions cannot find placements in a reasonable execution time as input designs increase in size. Heuristic solutions include meta-heuristics, such as Simulated Annealing (SA) and fast and straightforward greedy heuristics based on graph traversal. However, as these approaches are probabilistic and have a large design space, it is not easy to provide both run-time efficiency and good solution quality. We propose a graph traversal heuristic that provides the best of both: high-quality placements similar to SA and the execution time of graph traversal approaches. Our placement introduces novel ideas based on “you only traverse twice” (YOTT) approach that performs a two-step graph traversal. The first traversal generates annotated data to guide the second step, which greedily performs the placement, node per node, aided by the annotated data and target architecture constraints. We introduce three new concepts to implement this technique: I/O and reconvergence annotation, degree matching, and look-ahead placement. Our analysis of this approach explores the placement execution time/quality trade-offs. We point out insights on how to analyze graph properties during dataflow mapping. Our results show that YOTT is 60.6 , 9.7 , and 2.3 faster than a high-quality SA, bounding box SA VPR, and multi-single traversal placements, respectively. Furthermore, YOTT reduces the average wire length and the maximal FIFO size (additional timing requirement on CGRAs) to avoid delay mismatches in fully pipelined architectures.

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