When Are Software Verification Results Valid for Approximate Hardware?

2019 ◽  
pp. 3-20
Author(s):  
Tobias Isenberg ◽  
Marie-Christine Jakobs ◽  
Felix Pauck ◽  
Heike Wehrheim
Keyword(s):  
Software Verification

Synthesizing Conjunctive & Disjunctive Linear Invariants by K-means++ and SVM

2020 ◽  
Vol 17 (6) ◽  
pp. 847-856
Author(s):  
Shengbing Ren ◽  
Xiang Zhang
Keyword(s):  
Software Verification ◽  
State Of The Art ◽  
Positive Sample ◽  
Machine Learning Algorithms ◽  
Support Vector ◽  
Hoare Logic ◽  
Excellent Performance ◽  
Automated Software ◽  
Inductive Invariants ◽  
Linear Invariants

The problem of synthesizing adequate inductive invariants lies at the heart of automated software verification. The state-of-the-art machine learning algorithms for synthesizing invariants have gradually shown its excellent performance. However, synthesizing disjunctive invariants is a difficult task. In this paper, we propose a method k++ Support Vector Machine (SVM) integrating k-means++ and SVM to synthesize conjunctive and disjunctive invariants. At first, given a program, we start with executing the program to collect program states. Next, k++SVM adopts k-means++ to cluster the positive samples and then applies SVM to distinguish each positive sample cluster from all negative samples to synthesize the candidate invariants. Finally, a set of theories founded on Hoare logic are adopted to check whether the candidate invariants are true invariants. If the candidate invariants fail the check, we should sample more states and repeat our algorithm. The experimental results show that k++SVM is compatible with the algorithms for Intersection Of Half-space (IOH) and more efficient than the tool of Interproc. Furthermore, it is shown that our method can synthesize conjunctive and disjunctive invariants automatically

scholarly journals SAT modulo discrete event simulation applied to railway design capacity analysis

2021 ◽  
Author(s):  
Bjørnar Luteberget ◽  
Koen Claessen ◽  
Christian Johansen ◽  
Martin Steffen
Keyword(s):  
Discrete Event Simulation ◽  
Construction Projects ◽  
Software Verification ◽  
Ad Hoc ◽  
Discrete Event ◽  
Capacity Analysis ◽  
Railway Network ◽  
Event Simulation ◽  
Design Engineers ◽  
Railway Capacity

AbstractThis paper proposes a new method of combining SAT with discrete event simulation. This new integration proved useful for designing a solver for capacity analysis in early phase railway construction design. Railway capacity is complex to define and analyze, and existing tools and methods used in practice require comprehensive models of the railway network and its timetables. Design engineers working within the limited scope of construction projects report that only ad-hoc, experience-based methods of capacity analysis are available to them. Designs often have subtle capacity pitfalls which are discovered too late, only when network-wide timetables are made—there is a mismatch between the scope of construction projects and the scope of capacity analysis, as currently practiced. We suggest a language for capacity specifications suited for construction projects, expressing properties such as running time, train frequency, overtaking and crossing. Such specifications can be used as contracts in the interface between construction projects and network-wide capacity analysis. We show how these properties can be verified fully automatically by building a special-purpose solver which splits the problem into two: an abstracted SAT-based dispatch planning, and a continuous-domain dynamics with timing constraints evaluated using discrete event simulation. The two components communicate in a CEGAR loop (counterexample-guided abstraction refinement). This architecture is beneficial because it clearly distinguishes the combinatorial choices on the one hand from continuous calculations on the other, so that the simulation can be extended by relevant details as needed. We describe how loops in the infrastructure can be handled to eliminate repeating dispatch plans, and use case studies based on data from existing infrastructure and ongoing construction projects to show that our method is fast enough at relevant scales to provide agile verification in a design setting. Similar SAT modulo discrete event simulation combinations could also be useful elsewhere where one or both of these methods are already applicable such as in bioinformatics or hardware/software verification.

scholarly journals Software Verification and Validation of Safe Autonomous Cars: A Systematic Literature Review

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 4797-4819
Author(s):  
Nijat Rajabli ◽  
Francesco Flammini ◽  
Roberto Nardone ◽  
Valeria Vittorini
Keyword(s):  
Literature Review ◽  
Systematic Literature Review ◽  
Software Verification ◽  
Verification And Validation ◽  
Autonomous Cars ◽  
Software Verification And Validation

Establishing an Efficient Test Framework for Embedded Software Verification via Hardware-in-the-Loop Testing

2012 ◽  
Author(s):  
Daniel Kang ◽  
David Zhang ◽  
William Fleming ◽  
James Fron ◽  
Vivek Jaikamal
Keyword(s):  
Software Verification ◽  
Embedded Software ◽  
Hardware In The Loop ◽  
Efficient Test ◽  
Test Framework

Certification and Software Verification Considerations for Autonomous Unmanned Aircraft

2014 ◽  
Vol 11 (10) ◽  
pp. 649-664 ◽  
Author(s):  
Christoph Torens ◽  
Florian-M. Adolf ◽  
Lukas Goormann
Keyword(s):  
Software Verification ◽  
Unmanned Aircraft
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