FPGA Implementation of Outer Decoders for Sequential Decoder of Polar Codes

Author(s):  
Nikita Makarov ◽  
Aleksei Krylov ◽  
Andrey Rashich ◽  
Nguyen Ngoc Tan
2021 ◽  
pp. 104264
Author(s):  
Federico G. Krasser ◽  
Mónica C. Liberatori ◽  
Leonardo Coppolillo ◽  
Leonardo Arnone ◽  
Jorge Castiñeira Moreira

Author(s):  
G. Aparna ◽  
Raparla Swathi ◽  
M. Kezia Joseph ◽  
C.N. Sujatha ◽  
B. Rajendra Naik

Author(s):  
C.N. Sujatha ◽  
B. Rajendra Naik ◽  
M. Kezia Joseph ◽  
G. Aparna ◽  
Raparla Swathi

An emerging error-detection and correcting technique developed in the recent years is Polar codes. The technique does not focus on randomization of the bits like other techniques does, but is based on the Shannon theory and channel polarization. This paper presents a successive cancellation (SC) algorithm based FPGA implementation of Polar codes. The implementation focuses on low complexity decoder for high speed applications. Software Simulation outcomes represent the execution to polar codes can outperform those are turbo or LDPC codes.


2013 ◽  
Vol 5 (1) ◽  
pp. 36-41
Author(s):  
R. Ganesh ◽  
◽  
Ch. Sandeep Reddy ◽  

Author(s):  
Jeniffer A ◽  
Haripasath S ◽  
Chinthamani S ◽  
Chitra G ◽  
Karthiga V

2019 ◽  
Vol 12 (1) ◽  
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Badr El Kari ◽  
Hassan Ayad ◽  
Abdeljalil El Kari ◽  
Mostafa Mjahed ◽  
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2020 ◽  
Vol E103.B (1) ◽  
pp. 43-51 ◽  
Author(s):  
Yuhuan WANG ◽  
Hang YIN ◽  
Zhanxin YANG ◽  
Yansong LV ◽  
Lu SI ◽  
...  

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