2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)
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Published By IEEE

9781479979264

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Improvement in error resilience for compressed VLSI test data using Hamming code based technique

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050494 ◽

2015 ◽

Author(s):

Usha Sandeep Mehta ◽

Harikrishna Parmar

Keyword(s):

Test Data ◽

Error Resilience ◽

Hamming Code ◽

Vlsi Test

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Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050468 ◽

2015 ◽

Cited By ~ 1

Author(s):

Havisha Kalwad ◽

Sompally Neeharika ◽

Songa Divya ◽

M. Vinodhini ◽

N.S. Murty

Keyword(s):

Error Control ◽

Network On Chip ◽

Adaptive Error Control ◽

On Chip

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A real time watermarking of grayscale images without altering it's content

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050469 ◽

2015 ◽

Cited By ~ 5

Author(s):

Sakthivel S.M. ◽

Ravi Sankar A.

Keyword(s):

Real Time ◽

Grayscale Images

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On-chip comparison based secure output response compactor for scan-based attack resistance

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050467 ◽

2015 ◽

Cited By ~ 1

Author(s):

Sudeendra kumar K ◽

Kalpesh Lodha ◽

Sauvagya Ranjan Sahoo ◽

K.K. Mahapatra

Keyword(s):

Output Response ◽

On Chip

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Low power and high performance MOSFET

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050455 ◽

2015 ◽

Author(s):

Veera Boopathy E ◽

Raghul G. ◽

Karthick K.

Keyword(s):

Low Power ◽

High Performance

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Performance analysis of various scheduling algorithms using FPGA platforms

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050477 ◽

2015 ◽

Author(s):

Liyaqat Nazir ◽

Roohie Naaz Mir

Keyword(s):

Performance Analysis ◽

Scheduling Algorithms

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Improved single image and video dehazing using morphological operation

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050486 ◽

2015 ◽

Cited By ~ 1

Author(s):

Apurva Kumari ◽

Sidharth Sahdev ◽

S.K. Sahoo

Keyword(s):

Morphological Operation ◽

Single Image

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An 8-b 250-Msample/s power optimized pipelined A/D converter in 0.18-µm CMOS

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050479 ◽

2015 ◽

Author(s):

Manas Kumar Hati ◽

Tarun K. Bhattacharyya

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FPGA implementation of an advanced encoding and decoding architecture of polar codes

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050456 ◽

2015 ◽

Cited By ~ 9

Author(s):

Mamatha Sarah Oommen ◽

S. Ravishankar

Keyword(s):

Fpga Implementation ◽

Polar Codes

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Intermediate representation for heterogeneous multi-core: A survey

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050496 ◽

2015 ◽

Cited By ~ 1

Author(s):

Meena Belwal ◽

Sudarshan TSB

Keyword(s):

Intermediate Representation

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2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Improvement in error resilience for compressed VLSI test data using Hamming code based technique

Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches

A real time watermarking of grayscale images without altering it's content

On-chip comparison based secure output response compactor for scan-based attack resistance

Low power and high performance MOSFET

Performance analysis of various scheduling algorithms using FPGA platforms

Improved single image and video dehazing using morphological operation

An 8-b 250-Msample/s power optimized pipelined A/D converter in 0.18-µm CMOS

FPGA implementation of an advanced encoding and decoding architecture of polar codes

Intermediate representation for heterogeneous multi-core: A survey

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)
Latest Publications