scholarly journals Faster Binary-Field Multiplication and Faster Binary-Field MACs

2014 ◽  
pp. 92-111 ◽  
Author(s):  
Daniel J. Bernstein ◽  
Tung Chou
Keyword(s):  
Binary Field ◽  
Field Multiplication

Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials

2012 ◽  
Vol 20 (3) ◽  
pp. 449-458 ◽  
Author(s):  
M. Anwar Hasan ◽  
Ashkan Hosseinzadeh Namin ◽  
Christophe Negre
Keyword(s):  
Toeplitz Matrix ◽  
Matrix Approach ◽  
Binary Field ◽  
Field Multiplication

scholarly journals Highly Efficient SCA-Resistant Binary Field Multiplication on 8-Bit AVR Microcontrollers

2020 ◽  
Vol 10 (8) ◽  
pp. 2821
Author(s):  
Seog Chung Seo ◽  
Donggeun Kwon
Keyword(s):  
Performance Improvement ◽  
Power Analysis ◽  
Timing Analysis ◽  
Block Size ◽  
Optimization Techniques ◽  
Binary Field ◽  
Elliptic Curve Cryptosystems ◽  
Xor Operation ◽  
Improved Performance ◽  
Field Multiplication

Binary field ( B F ) multiplication is a basic and important operation for widely used crypto algorithms such as the GHASH function of GCM (Galois/Counter Mode) mode and NIST-compliant binary Elliptic Curve Cryptosystems (ECCs). Recently, Seo et al. proposed a novel SCA-resistant binary field multiplication method in the context of GHASH optimization in AES GCM mode on 8-bit AVR microcontrollers (MCUs). They proposed a concept of Dummy XOR operation with a kind of garbage registers and a concept of instruction level atomicity ( I L A ) for resistance against Timing Analysis (TA) and Simple Power Analysis (SPA) and used a Karatsuba Block-Comb multiplication approach for efficiency. Even though their method achieved a large performance improvement compared with previous works, it still has room for improvement on the 8-bit AVR platform. In this paper, we propose a more improved binary field multiplication method on 8-bit AVR MCUs. Our method basically adopts a Dummy XOR technique using a set of garbage registers for TA and SPA security; however, we save the number of used garbage registers from eight to one by using the fact that the number of used garbage registers does not affect TA and SPA security. In addition, we apply a multiplier encoding approach so as to decrease the number of required registers when accessing the multiplier, which enables the use of extended block size in the Karatsuba Block-Comb multiplication technique. Actually, the proposed technique extends the block size from four to eight and the proposed binary field multiplication method can compute a 128-bit B F multiplication with only 3816 clock cycles ( c c ) (resp. 3490 c c ) with (resp. without) the multiplier encoding process, which is almost a 32.8% (resp. 38.5%) improvement compared with 5675 c c of the best previous work. We apply the proposed technique to the GHASH function of the GCM mode with several additional optimization techniques. The proposed GHASH implementation provides improved performance by over 42% compared with the previous best result. The concept of the proposed B F method can be extended to other MCUs, including 16-bit MSP430 MCUs and 32-bit ARM MCUs.

scholarly journals Block Recombination Approach for Subquadratic Space Complexity Binary Field Multiplication Based on Toeplitz Matrix-Vector Product

2012 ◽  
Vol 61 (2) ◽  
pp. 151-163 ◽  
Author(s):  
M. Anwar Hasan ◽  
Nicolas Meloni ◽  
Ashkan H. Namin ◽  
Christophe Negre
Keyword(s):  
Toeplitz Matrix ◽  
Space Complexity ◽  
Vector Product ◽  
Binary Field ◽  
Field Multiplication ◽  
Matrix Vector

scholarly journals Secure Binary Field Multiplication

2016 ◽  
pp. 161-173 ◽  
Author(s):  
Hwajeong Seo ◽  
Chien-Ning Chen ◽  
Zhe Liu ◽  
Yasuyuki Nogami ◽  
Taehwan Park ◽  
...  
Keyword(s):  
Binary Field ◽  
Field Multiplication

scholarly journals Binary field multiplication on ARMv8

2016 ◽  
Vol 9 (13) ◽  
pp. 2051-2058 ◽  
Author(s):  
Hwajeong Seo ◽  
Zhe Liu ◽  
Yasuyuki Nogami ◽  
Jongseok Choi ◽  
Howon Kim
Keyword(s):  
Binary Field ◽  
Field Multiplication
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