Self-loop Pipelining and Reconfigurable Dataflow Arrays

Lecture Notes in Computer Science - Computer Systems: Architectures, Modeling, and Simulation ◽

10.1007/978-3-540-27776-7_25 ◽

2004 ◽

pp. 234-243 ◽

Author(s):

João M. P. Cardoso

Keyword(s):

Loop Pipelining

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Forwarding Unit Generation for Loop Pipelining in High-level Synthesis

IPSJ Transactions on System LSI Design Methodology ◽

10.2197/ipsjtsldm.7.119 ◽

2014 ◽

Vol 7 (0) ◽

pp. 119-124

Author(s):

Shingo Kusakabe ◽

Kenshu Seto

Keyword(s):

High Level Synthesis ◽

Loop Pipelining ◽

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Scheduling Algorithms for Compiler of Loop Pipelining Designs on FPGAs

International Journal of Advancements in Computing Technology ◽

10.4156/ijact.vol4.issue23.9 ◽

2012 ◽

Vol 4 (23) ◽

pp. 67-78 ◽

Author(s):

Lu Zhijian ◽

Wu Yanxia ◽

Guo Zhenhua ◽

Gu Guochang

Keyword(s):

Scheduling Algorithms ◽

Loop Pipelining

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Resource constrained algebraic transformation for loop pipelining

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497585 ◽

2002 ◽

Author(s):

Jian-Feng Shi ◽

Liang-Fang Chao

Keyword(s):

Resource Constrained ◽

Algebraic Transformation ◽

Loop Pipelining

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Enabling adaptive loop pipelining in high-level synthesis

2017 51st Asilomar Conference on Signals, Systems, and Computers ◽

10.1109/acssc.2017.8335152 ◽

2017 ◽

Author(s):

Steve Dai ◽

Gai Liu ◽

Ritchie Zhao ◽

Zhiru Zhang

Keyword(s):

High Level Synthesis ◽

Loop Pipelining ◽

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Unifying Fixed Code Mapping, Communication, Synchronization and Scheduling Algorithms for Efficient and Scalable Loop Pipelining

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/tpds.2018.2817207 ◽

2018 ◽

Vol 29 (9) ◽

pp. 2136-2149 ◽

Author(s):

Aristeidis Mastoras ◽

Thomas R. Gross

Keyword(s):

Scheduling Algorithms ◽

Loop Pipelining

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Runtime dependency analysis for loop pipelining in high-level synthesis

Proceedings of the 50th Annual Design Automation Conference on - DAC '13 ◽

10.1145/2463209.2488796 ◽

2013 ◽

Author(s):

Mythri Alle ◽

Antoine Morvan ◽

Steven Derrien

Keyword(s):

High Level Synthesis ◽

Dependency Analysis ◽

Loop Pipelining ◽

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Combining MBP-speculative computation and loop pipelining in high-level synthesis

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470346 ◽

2002 ◽

Author(s):

U. Holtmann ◽

R. Ernst

Keyword(s):

High Level Synthesis ◽

Loop Pipelining ◽

Speculative Computation ◽

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Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2014.6908397 ◽

2014 ◽

Author(s):

Bing Xu ◽

Shouyi Yin ◽

Leibo Liu ◽

Shaojun Wei

Keyword(s):

Low Power ◽

Loop Pipelining

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Data Parallelism Optimization for the CGRA Loop Pipelining Mapping

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2013.01280 ◽

2014 ◽

Vol 36 (6) ◽

pp. 1280-1289 ◽

Author(s):

Zi-Yu YANG ◽

Ming YAN ◽

Da-Wei WANG ◽

Si-Kun LI

Keyword(s):

Data Parallelism ◽

Loop Pipelining

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Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2953879 ◽

2017 ◽

Vol 22 (2) ◽

pp. 1-22 ◽

Author(s):

Mohammad Reza Azarbad ◽

Bijan Alizadeh

Keyword(s):

Equivalence Checking ◽

Behavioral Synthesis ◽

Loop Pipelining ◽

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