Proceedings the European Design and Test Conference. ED&TC 1995
Latest Publications

TOTAL DOCUMENTS

113

(FIVE YEARS 0)

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Published By IEEE Comput. Soc. Press

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A built-in quiescent current monitor for CMOS VLSI circuits

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470341 ◽

2002 ◽

Cited By ~ 13

Author(s):

A. Rubio ◽

E. Janssens ◽

H. Casier ◽

J. Figueras ◽

D. Mateo ◽

...

Keyword(s):

Vlsi Circuits ◽

Quiescent Current ◽

Cmos Vlsi

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High speed communications links for ASICs

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470340 ◽

2002 ◽

Author(s):

I. Montandon ◽

D. Burrows ◽

K. Hunt

Keyword(s):

High Speed

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Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470342 ◽

2002 ◽

Cited By ~ 4

Author(s):

H.-J. Wunderlich ◽

M. Herzog ◽

J. Figueras ◽

J.A. Carrasco ◽

A. Calderon

Keyword(s):

Current Sensors

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Direct performance-driven placement of mismatch-sensitive analog circuits

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470332 ◽

2002 ◽

Cited By ~ 1

Author(s):

K. Lampaert ◽

G. Gielen ◽

W. Sansen

Keyword(s):

Analog Circuits

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Network initialization in a switch-level simulator

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470333 ◽

2002 ◽

Author(s):

A.J. van Genderen

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A balanced multilevel decomposition method

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470335 ◽

2002 ◽

Author(s):

H. Selvaraj ◽

T. Luba

Keyword(s):

Decomposition Method

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A precise event-driven circuit simulator based on predicted fan-in voltages

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470334 ◽

2002 ◽

Cited By ~ 1

Author(s):

H. Fujisawa ◽

F. Kawafuji ◽

T. Kitaura ◽

T. Kage

Keyword(s):

Circuit Simulator ◽

Event Driven

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Rapid prototype of a hardware emulator for a SIMD processor array

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470366 ◽

2002 ◽

Author(s):

D.L. Andrews ◽

A. Wheeler ◽

B. Wealand ◽

C. Kancler

Keyword(s):

Rapid Prototype ◽

Processor Array ◽

Hardware Emulator

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The effect of pin constraints on layout area

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470317 ◽

2002 ◽

Author(s):

B. Schurmann ◽

J. Altmeyer

Keyword(s):

Layout Area

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Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470336 ◽

2002 ◽

Cited By ~ 9

Author(s):

B. Becker ◽

R. Drechsler

Keyword(s):

Decision Diagrams ◽

Synthesis For Testability

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Proceedings the European Design and Test Conference. ED&TC 1995Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

A built-in quiescent current monitor for CMOS VLSI circuits

High speed communications links for ASICs

Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors

Direct performance-driven placement of mismatch-sensitive analog circuits

Network initialization in a switch-level simulator

A balanced multilevel decomposition method

A precise event-driven circuit simulator based on predicted fan-in voltages

Rapid prototype of a hardware emulator for a SIMD processor array

The effect of pin constraints on layout area

Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams

Proceedings the European Design and Test Conference. ED&TC 1995
Latest Publications