Proceedings of the Sixth Great Lakes Symposium on VLSI
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Published By IEEE Comput. Soc. Press

0818675020

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An accurate interconnection length estimation for computer logic

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497592 ◽

2002 ◽

Cited By ~ 13

Author(s):

D. Strooband ◽

H. Van Marck ◽

J. Van Campenhout

Keyword(s):

Length Estimation ◽

Computer Logic

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Resource constrained algebraic transformation for loop pipelining

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497585 ◽

2002 ◽

Cited By ~ 2

Author(s):

Jian-Feng Shi ◽

Liang-Fang Chao

Keyword(s):

Resource Constrained ◽

Algebraic Transformation ◽

Loop Pipelining

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Partitioning algorithms for corner stitching [VLSI]

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497620 ◽

2002 ◽

Author(s):

M.A. Lopez ◽

D.P. Mehta

Keyword(s):

Partitioning Algorithms

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Test generation for networks of interacting FSMs using symbolic techniques

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497621 ◽

2002 ◽

Cited By ~ 5

Author(s):

F. Ferrandi ◽

F. Fummi ◽

E. Macii ◽

M. Poncino ◽

D. Sciuto

Keyword(s):

Test Generation

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A 1.0 ns 64-bits GaAs adder using quad tree algorithm

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497587 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Royannez ◽

A. Amara

Keyword(s):

Tree Algorithm ◽

Quad Tree

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Synthesis of real-time recursive DSP algorithms using multiple chips

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497584 ◽

2002 ◽

Cited By ~ 1

Author(s):

Duen-Jeng Wang ◽

Yu Hen Hu

Keyword(s):

Real Time

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Exact computation of the entropy of a logic circuit

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497613 ◽

2002 ◽

Cited By ~ 7

Author(s):

E. Macii ◽

M. Poncino

Keyword(s):

Logic Circuit ◽

Exact Computation

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A hierarchical approach for power reduction in VLSI chips

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497617 ◽

2002 ◽

Author(s):

P. Arunachalam ◽

J. Abraham ◽

M. d'Abreu

Keyword(s):

Power Reduction ◽

Hierarchical Approach ◽

Vlsi Chips

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Recent developments in performance driven Steiner routing: an overview

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497609 ◽

2002 ◽

Author(s):

M. Borah ◽

R.M. Owens ◽

M.J. Irwin

Keyword(s):

Recent Developments

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A parametrical architecture for Reed-Solomon decoders

Proceedings of the Sixth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1996.497598 ◽

2002 ◽

Cited By ~ 2

Author(s):

M.-E. Petre ◽

G. Masera

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Proceedings of the Sixth Great Lakes Symposium on VLSILatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

An accurate interconnection length estimation for computer logic

Resource constrained algebraic transformation for loop pipelining

Partitioning algorithms for corner stitching [VLSI]

Test generation for networks of interacting FSMs using symbolic techniques

A 1.0 ns 64-bits GaAs adder using quad tree algorithm

Synthesis of real-time recursive DSP algorithms using multiple chips

Exact computation of the entropy of a logic circuit

A hierarchical approach for power reduction in VLSI chips

Recent developments in performance driven Steiner routing: an overview

A parametrical architecture for Reed-Solomon decoders

Proceedings of the Sixth Great Lakes Symposium on VLSI
Latest Publications