Reduction of Interrupt Handler Executions for Model Checking Embedded Software

Author(s):  
Bastian Schlich ◽  
Thomas Noll ◽  
Jörg Brauer ◽  
Lucas Brutschy
2012 ◽  
Vol 19 (1) ◽  
pp. 39-68 ◽  
Author(s):  
Rodrigo Pastl Pontes ◽  
Paulo Claudino Véras ◽  
Ana Maria Ambrosio ◽  
Emília Villani

2013 ◽  
Vol 25 (1) ◽  
pp. 126-136
Author(s):  
Waldo A. F. Alencar ◽  
Emilia Villani

Author(s):  
Xianghua Deng ◽  
Matthew B. Dwyer ◽  
John Hatcliff ◽  
Georg Jung ◽  
Robby ◽  
...  

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1060
Author(s):  
Satoshi Yamane ◽  
Junpei Kobashi ◽  
Kosuke Uemura

Embedded software has properties dependent on hardware (direct operation of address spaces, memory mapped I/O, interruption, etc.). Therefore, demands about the established method of formal verifications corresponding to those properties are increasing from the point of view of shorter development and high reliability. Our study aims at enabling a formal verification with Satisfiability Modulo Theories-Based Bounded Model Checking (SMT-Based BMC) of safety for embedded assembly codes. Our proposed method generates models of assembly codes in detail with the fixed-sized bit-vectors theory. The models generated by our method include interrupts, and the size of the models is reduced using Interrupt Handler Execution Reduction (IHER) technique. In this paper, we have developed the verification method of safety properties of embedded assembly program by combining SMT-Based Bounded Model Checking and Reduction of Interrupt Handler Executions. Moreover, we show the evaluation of our method by experiments using prototype model checker.


Author(s):  
Eduard P. Enoiu ◽  
Daniel Sundmark ◽  
Adnan Čaušević ◽  
Robert Feldt ◽  
Paul Pettersson

Author(s):  
Thomas Reinbacher ◽  
Martin Horauer ◽  
Bastian Schlich ◽  
Jorg Brauer ◽  
Florian Scheuer

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