scholarly journals Verification Method of Safety Properties of Embedded Assembly Program by Combining SMT-Based Bounded Model Checking and Reduction of Interrupt Handler Executions

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1060
Author(s):  
Satoshi Yamane ◽  
Junpei Kobashi ◽  
Kosuke Uemura
Keyword(s):  
Model Checking ◽  
High Reliability ◽  
Bounded Model Checking ◽  
Point Of View ◽  
Satisfiability Modulo Theories ◽  
Prototype Model ◽  
Safety Properties ◽  
Verification Method ◽  
Interrupt Handler ◽  
Direct Operation

Embedded software has properties dependent on hardware (direct operation of address spaces, memory mapped I/O, interruption, etc.). Therefore, demands about the established method of formal verifications corresponding to those properties are increasing from the point of view of shorter development and high reliability. Our study aims at enabling a formal verification with Satisfiability Modulo Theories-Based Bounded Model Checking (SMT-Based BMC) of safety for embedded assembly codes. Our proposed method generates models of assembly codes in detail with the fixed-sized bit-vectors theory. The models generated by our method include interrupts, and the size of the models is reduced using Interrupt Handler Execution Reduction (IHER) technique. In this paper, we have developed the verification method of safety properties of embedded assembly program by combining SMT-Based Bounded Model Checking and Reduction of Interrupt Handler Executions. Moreover, we show the evaluation of our method by experiments using prototype model checker.

scholarly journals Dartagnan: Bounded Model Checking for Weak Memory Models (Competition Contribution)

2020 ◽  
pp. 378-382
Author(s):  
Hernán Ponce-de-León ◽  
Florian Furbach ◽  
Keijo Heljanko ◽  
Roland Meyer
Keyword(s):  
Model Checking ◽  
Bounded Model Checking ◽  
Memory Models ◽  
Memory Model ◽  
Complete Analysis ◽  
Concurrent Programs ◽  
Sequential Consistency ◽  
Model Checker ◽  
Safety Properties ◽  
C Programs

Abstract Dartagnanis a bounded model checker for concurrent programs under weak memory models. What makes it different from other tools is that the memory model is not hard-coded inside Dartagnanbut taken as part of the input. For SV-COMP’20, we take as input sequential consistency (i.e. the standard interleaving memory model) extended by support for atomic blocks. Our point is to demonstrate that a universal tool can be competitive and perform well in SV-COMP. Being a bounded model checker, Dartagnan’s focus is on disproving safety properties by finding counterexample executions. For programs with bounded loops, Dartagnanperforms an iterative unwinding that results in a complete analysis. The SV-COMP’20 version of Dartagnanworks on Boogiecode. The C programs of the competition are translated internally to Boogieusing SMACK.

scholarly journals EPR-based k-induction with Counterexample Guided Abstraction Refinement

10.29007/scv7 ◽  
2018 ◽  
Author(s):  
Zurab Khasidashvili ◽  
Konstantin Korovin ◽  
Dmitry Tsarkov
Keyword(s):  
Model Checking ◽  
Bounded Model Checking ◽  
Order Logic ◽  
Experimental Results ◽  
Theorem Prover ◽  
First Order Logic ◽  
Safety Properties ◽  
Abstraction Refinement ◽  
First Order ◽  
Automated Theorem Prover

In recent years it was proposed to encode bounded model checking (BMC) into the effectively propositional fragment of first-order logic (EPR). The EPR fragment can provide for a succinct representation of the problem and facilitate reasoning at a higher level.In this paper we present an extension of the EPR-based bounded model checkingwith k-induction which can be used to prove safety properties of systems overunbounded runs. We present a novel abstraction-refinement approach based onunsatisfiable cores and models (UCM) for BMC and k-induction in the EPR setting.We have implemented UCM refinements for EPR-based BMC and k-induction in a first-order automated theorem prover iProver. We also extended iProver with the AIGER format and evaluated it over the HWMCC'14 competition benchmarks. The experimental results are encouraging. We show that a number of AIG problems can be verified until deeper bounds with the EPR-based model checking.

scholarly journals SMT Encoding of Hybrid Systems in dReal

10.29007/s3b9 ◽  
2018 ◽  
Author(s):  
Kyungmin Bae ◽  
Soonho Kong ◽  
Sicun Gao
Keyword(s):  
Model Checking ◽  
Differential Equations ◽  
Ordinary Differential Equations ◽  
Hybrid Systems ◽  
Bounded Model Checking ◽  
Satisfiability Modulo Theories ◽  
Real Numbers ◽  
The Real ◽  
Real Functions ◽  
Nonlinear Hybrid

Analysis problems of hybrid systems, involving nonlinear real functions and ordinary differential equations, can be reduced to SMT (satisfiability modulo theories) problems over the real numbers. The dReal solver can automatically check the satisfiability of such SMT formulas up to a given precision δ > 0. This paper explains how bounded model checking problems of hybrid systems are encoded in dReal. In particular, a novel SMT syntax of dReal enables to effectively represent networks of hybrid systems in a modular way. We illustrate SMT encoding in dReal with simple nonlinear hybrid systems.

Bounded Model Checking for Probabilistic Computation Tree Logic

2012 ◽  
Vol 23 (7) ◽  
pp. 1656-1668 ◽  
Author(s):  
Cong-Hua ZHOU ◽  
Zhi-Feng LIU ◽  
Chang-Da WANG
Keyword(s):  
Model Checking ◽  
Bounded Model Checking ◽  
Probabilistic Computation ◽  
Computation Tree Logic ◽  
Computation Tree

Bounded model checking of high-integrity software

2013 ◽  
Vol 33 (3) ◽  
pp. 9-10
Author(s):  
Sagar Chaki
Keyword(s):  
Model Checking ◽  
Bounded Model Checking ◽  
High Integrity

scholarly journals Contradictory antecedent debugging in bounded model checking

2009 ◽  
Author(s):  
Daniel Grosse ◽  
Robert Wille ◽  
Ulrich Kuehne ◽  
Rolf Drechsler
Keyword(s):  
Model Checking ◽  
Bounded Model Checking
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