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Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science
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10.1007/978-3-642-24154-3_28
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2011
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pp. 278-287
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Cited By ~ 3
Author(s):
Amir-Mohammad Rahmani
◽
Kameswar Rao Vaddina
◽
Pasi Liljeberg
◽
Juha Plosila
◽
Hannu Tenhunen
Keyword(s):
Networks On Chip
◽
Area Optimization
◽
On Chip
◽
3D Networks
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References
Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip
Embedded Systems
◽
10.1002/9781118468654.ch10
◽
2012
◽
pp. 239-258
Author(s):
Sudeep Pasricha
◽
Yong Zou
Keyword(s):
Fault Tolerant
◽
Networks On Chip
◽
On Chip
◽
3D Networks
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Exploring a low-cost inter-layer communication scheme for 3D networks-on-chip
2010 15th CSI International Symposium on Computer Architecture and Digital Systems
◽
10.1109/cads.2010.5623588
◽
2010
◽
Cited By ~ 3
Author(s):
Amir-Mohammad Rahmani
◽
Pasi Liljeberg
◽
Juha Plosila
◽
Hannu Tenhunen
Keyword(s):
Low Cost
◽
Networks On Chip
◽
Communication Scheme
◽
On Chip
◽
3D Networks
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G-CARA: A Global Congestion-Aware Routing Algorithm for traffic management in 3D networks-on-chip
2017 Iranian Conference on Electrical Engineering (ICEE)
◽
10.1109/iraniancee.2017.7985425
◽
2017
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Cited By ~ 5
Author(s):
Nooshin Nosrati
◽
Hadi Shahriar Shahhoseini
Keyword(s):
Traffic Management
◽
Routing Algorithm
◽
Networks On Chip
◽
On Chip
◽
3D Networks
◽
Congestion Aware
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An adaptive router architecture for heterogeneous 3D Networks-on-Chip
2011 NORCHIP
◽
10.1109/norchp.2011.6126725
◽
2011
◽
Cited By ~ 3
Author(s):
Michael Opoku Agyeman
◽
Ali Ahmadinia
Keyword(s):
Networks On Chip
◽
Router Architecture
◽
On Chip
◽
3D Networks
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3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip
2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
◽
10.1109/patmos.2017.8106980
◽
2017
◽
Cited By ~ 3
Author(s):
K. Tatas
◽
S. Savva
◽
C. Kyriacou
Keyword(s):
Networks On Chip
◽
On Chip
◽
3D Networks
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Optimising Heterogeneous 3D Networks-on-Chip
2011 Sixth International Symposium on Parallel Computing in Electrical Engineering
◽
10.1109/parelec.2011.40
◽
2011
◽
Cited By ~ 4
Author(s):
Michael Opoku Agyeman
◽
Ali Ahmadinia
Keyword(s):
Networks On Chip
◽
On Chip
◽
3D Networks
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Power and area optimisation in heterogeneous 3D networks-on-chip architectures
ACM SIGARCH Computer Architecture News
◽
10.1145/2082156.2082187
◽
2011
◽
Vol 39
(4)
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pp. 106-107
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Cited By ~ 1
Author(s):
Michael Opoku Agyeman
◽
Ali Ahmadinia
Keyword(s):
Networks On Chip
◽
On Chip
◽
3D Networks
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Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip
Journal of Systems Architecture
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10.1016/j.sysarc.2018.08.002
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2018
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Vol 89
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pp. 103-117
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Cited By ~ 14
Author(s):
Michael Opoku Agyeman
◽
Ali Ahmadinia
◽
Nader Bagherzadeh
Keyword(s):
Networks On Chip
◽
Application Mapping
◽
And Performance
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On Chip
◽
3D Networks
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Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
◽
10.1007/978-3-642-11802-9_13
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2010
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pp. 86-95
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Cited By ~ 4
Author(s):
Iraklis Anagnostopoulos
◽
Alexandros Bartzas
◽
Dimitrios Soudris
Keyword(s):
Networks On Chip
◽
Temperature Reduction
◽
Systematic Methodology
◽
Specific Temperature
◽
On Chip
◽
2D And 3D
◽
Application Specific
◽
3D Networks
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Abetting Planned Obsolescence by Aging 3D Networks-on-Chip
2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)
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10.1109/nocs.2018.8512162
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2018
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Author(s):
Sourav Das
◽
Kanad Basu
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Janardhan Rao Doppa
◽
Partha Pratim Pande
◽
Ramesh Karri
◽
...
Keyword(s):
Planned Obsolescence
◽
Networks On Chip
◽
On Chip
◽
3D Networks
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