A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-021-01814-1 ◽

2021 ◽

Author(s):

Hsin-Shu Chen ◽

Chien-Jian Tseng ◽

Cheng-Ming Chen ◽

Hsiang-Wen Chen

Keyword(s):

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Noise and error shaping for video applications pipeline ADC optimisation techniques

5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications ◽

10.1049/cp:20050141 ◽

2005 ◽

Author(s):

J. O'Donnell

Keyword(s):

Pipeline Adc ◽

Optimisation Techniques

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Design of a 1.8 V, 10-bit 130+MS/s time-interleaved non-scaled pipeline ADC in 0.18 μm CMOS

5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications ◽

10.1049/cp:20050125 ◽

2005 ◽

Author(s):

B. Vaz

Keyword(s):

Pipeline Adc ◽

Time Interleaved

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A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS

2020 IEEE Nordic Circuits and Systems Conference (NorCAS) ◽

10.1109/norcas51424.2020.9264994 ◽

2020 ◽

Author(s):

Timmy Sundstrom ◽

Javad Bagheri Asli ◽

Christer Svensson ◽

Atila Alvandpour

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A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431444 ◽

2021 ◽

Author(s):

Yanbo Zhang ◽

Jin Zhang ◽

Shubin Liu ◽

Zhangming Zhu ◽

Yan Zhu ◽

...

Keyword(s):

Noise Shaping ◽

Pipeline Adc ◽

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A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2020.3033931 ◽

2020 ◽

pp. 1-1

Author(s):

Yan Song ◽

Yan Zhu ◽

Chi-Hang Chan ◽

Rui P. Martins

Keyword(s):

Noise Shaping ◽

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A novel RSD correction for pipeline ADC

2011 9th IEEE International Conference on ASIC ◽

10.1109/asicon.2011.6157373 ◽

2011 ◽

Author(s):

Dawei Fu ◽

Lenian He ◽

Biye Xu

Keyword(s):

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A 65 nm CMOS Continuous-Time Pipeline ADC achieving 70 dB SNDR in 100 MHz Bandwidth

IEEE Solid-State Circuits Letters ◽

10.1109/lssc.2021.3071965 ◽

2021 ◽

pp. 1-1

Author(s):

Saravana Manivannan ◽

Shanthi Pavan

Keyword(s):

Continuous Time ◽

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A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2010.2050948 ◽

2010 ◽

Vol 57 (8) ◽

pp. 602-606 ◽

Author(s):

Kailash Chandrashekar ◽

Marco Corsi ◽

John Fattaruso ◽

Bertan Bakkaloglu

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Noiseless MOS parametric amplification in pipeline ADC

2011 3rd International Conference on Electronics Computer Technology ◽

10.1109/icectech.2011.5941757 ◽

2011 ◽

Author(s):

D. S. Shylu ◽

D. Jackuline Moni ◽

D. David Rajendra Prasad ◽

T. Suganya ◽

Ninu Prakash

Keyword(s):

Parametric Amplification ◽

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A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2004.836232 ◽

2004 ◽

Vol 39 (12) ◽

pp. 2139-2151 ◽

Author(s):

Yun Chiu ◽

P.R. Gray ◽

B. Nikolic

Keyword(s):

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