2021 IEEE Custom Integrated Circuits Conference (CICC)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 94)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781728175812

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Committees

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431538 ◽

2021 ◽

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A Battery-Connected Inductor-First Flying Capacitor Multilevel Converter Achieving 0.77W/mm2 and 97.1% Peak Efficiency

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431399 ◽

2021 ◽

Author(s):

Abdullah Abdulslam ◽

Patrick P. Mercier

Keyword(s):

Multilevel Converter ◽

Peak Efficiency

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A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431559 ◽

2021 ◽

Author(s):

Rakshith Saligram ◽

Divya Prasad ◽

David Pietromonaco ◽

Arijit Raychowdhury ◽

Brian Cline

Keyword(s):

Cryogenic Temperatures ◽

Design Technology ◽

And Performance

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An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431447 ◽

2021 ◽

Author(s):

Wei Deng ◽

Haikun Jia ◽

Rui Wu ◽

Shiyan Sun ◽

Chenggang Li ◽

...

Keyword(s):

Dual Core

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An Ultra-Compact 84.9-107GHz LNA with 4.9dB NF by Utilizing Coupled-line-based Gm-Boosting and Noise-Canceling Techniques in 65-nm CMOS Technology

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431407 ◽

2021 ◽

Author(s):

Wei Zhu ◽

Jiawen Wang ◽

Ruitao Wang ◽

Yan Wang

Keyword(s):

Cmos Technology ◽

Coupled Line ◽

Noise Canceling

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A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431444 ◽

2021 ◽

Author(s):

Yanbo Zhang ◽

Jin Zhang ◽

Shubin Liu ◽

Zhangming Zhu ◽

Yan Zhu ◽

...

Keyword(s):

Noise Shaping ◽

Pipeline Adc ◽

Over Time

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Zero-Crossing-Based Bio-Engineered Sensor

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431409 ◽

2021 ◽

Author(s):

Qijun Liu ◽

Arslan Riaz ◽

Timur Zirtiloglu ◽

Maria Eugenia Inda ◽

Miguel Jimenez ◽

...

Keyword(s):

Zero Crossing

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A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431475 ◽

2021 ◽

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Low Cost ◽

Sar Adc ◽

Mismatch Error

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A 20 μ W, 0.05mm2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing Systems

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431533 ◽

2021 ◽

Author(s):

Jinyong Kim ◽

Callen Votzke ◽

Soumya Bose ◽

Arun Natarajan ◽

Matthew L. Johnston

Keyword(s):

Wheatstone Bridge ◽

Low Resistance ◽

Sensing Systems

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Integrated-Circuit Node for Time-Domain Near-infrared Diffuse Optical Tomography Imaging Arrays with On-chip Histogramming and Integrated VCSELs

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431526 ◽

2021 ◽

Author(s):

Sajjad Moazeni ◽

Kevin Renehan ◽

Eric H. Pollmann ◽

Kenneth L. Shepard

Keyword(s):

Time Domain ◽

Integrated Circuit ◽

Near Infrared ◽

Optical Tomography ◽

Diffuse Optical Tomography ◽

Imaging Arrays ◽

Tomography Imaging ◽

On Chip

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2021 IEEE Custom Integrated Circuits Conference (CICC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Committees

A Battery-Connected Inductor-First Flying Capacitor Multilevel Converter Achieving 0.77W/mm2 and 97.1% Peak Efficiency

A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance

An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator

An Ultra-Compact 84.9-107GHz LNA with 4.9dB NF by Utilizing Coupled-line-based Gm-Boosting and Noise-Canceling Techniques in 65-nm CMOS Technology

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

Zero-Crossing-Based Bio-Engineered Sensor

A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

A 20 μ W, 0.05mm2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing Systems

Integrated-Circuit Node for Time-Domain Near-infrared Diffuse Optical Tomography Imaging Arrays with On-chip Histogramming and Integrated VCSELs

2021 IEEE Custom Integrated Circuits Conference (CICC)
Latest Publications