Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

2015 ◽  
Vol 71 (12) ◽  
pp. 4446-4475 ◽  
Author(s):  
Achraf Ben Ahmed ◽  
Abderazek Ben Abdallah
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Future Generations ◽  
Photonic Network ◽  
Silicon Photonic ◽  
Hybrid Silicon ◽  
On Chip ◽  
Many Core

Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems

2016 ◽  
Vol 73 (4) ◽  
pp. 1567-1599 ◽  
Author(s):  
Michael Meyer ◽  
Yuichi Okuyama ◽  
Abderazek Ben Abdallah
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Photonic Network ◽  
On Chip ◽  
Many Core

scholarly journals Six-port optical switch for cluster-mesh photonic network-on-chip

Nanophotonics ◽  
2018 ◽  
Vol 7 (5) ◽  
pp. 827-835 ◽  
Author(s):  
Hao Jia ◽  
Ting Zhou ◽  
Yunchou Zhao ◽  
Yuhao Xia ◽  
Jincheng Dai ◽  
...  
Keyword(s):  
High Performance ◽  
Optical Switching ◽  
Optical Switch ◽  
Optical Signal ◽  
Network On Chip ◽  
Transmission Experiment ◽  
Photonic Network ◽  
Benes Network ◽  
On Chip ◽  
Spectral Responses

AbstractPhotonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

scholarly journals Hybrid Network-on-Chip: An Application-Aware Framework for Big Data

Complexity ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-11
Author(s):  
Juan Fang ◽  
Sitong Liu ◽  
Shijian Liu ◽  
Yanjin Cheng ◽  
Lu Yu
Keyword(s):  
Energy Efficiency ◽  
Big Data ◽  
Power Consumption ◽  
High Performance ◽  
Network On Chip ◽  
Hybrid Network ◽  
Big Data Applications ◽  
Application Aware ◽  
On Chip ◽  
Many Core

Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data. Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount. To narrow the gap, a heterogamous design gives us a hint. A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect system energy efficiency. Among all the challenges in NoC, unaware application behaviors bring about considerable congestion, which wastes huge amounts of bandwidth and power consumption on the chip. In this paper, we propose a hybrid NoC framework, combining buffered and bufferless NoCs, to make the NoC framework aware of applications’ performance demands. An optimized congestion control scheme is also devised to satisfy the requirement in energy efficiency and the fairness of big data applications. We use a trace-driven simulator to model big data applications. Compared with the classical buffered NoC, the proposed hybrid NoC is able to significantly improve the performance of mixed applications by 17% on average and 24% at the most, decrease the power consumption by 38%, and improve the fairness by 13.3%.

Reconfigurable 100  Gb/s Silicon Photonic Network-on-Chip [Invited]

2014 ◽  
Vol 7 (1) ◽  
pp. A37 ◽  
Author(s):  
Po Dong ◽  
Young-Kai Chen ◽  
Tingyi Gu ◽  
Lawrence L. Buhl ◽  
David T. Neilson ◽  
...  
Keyword(s):  
Network On Chip ◽  
Photonic Network ◽  
Silicon Photonic ◽  
On Chip

scholarly journals 8 × 8 × 40  Gbps fully integrated silicon photonic network on chip

Optica ◽  
2016 ◽  
Vol 3 (7) ◽  
pp. 785 ◽  
Author(s):  
Chong Zhang ◽  
Shangjian Zhang ◽  
Jon D. Peters ◽  
John E. Bowers
Keyword(s):  
Network On Chip ◽  
Fully Integrated ◽  
Photonic Network ◽  
Silicon Photonic ◽  
On Chip

scholarly journals Mode-Division Multiplexing for Silicon Photonic Network-on-Chip

2017 ◽  
Vol 35 (15) ◽  
pp. 3223-3228 ◽  
Author(s):  
Xinru Wu ◽  
Chaoran Huang ◽  
Ke Xu ◽  
Chester Shu ◽  
Hon Ki Tsang
Keyword(s):  
Network On Chip ◽  
Mode Division Multiplexing ◽  
Photonic Network ◽  
Silicon Photonic ◽  
On Chip

Reconfigurable 100 Gb/s Silicon Photonic Network-on-Chip

2014 ◽  
Author(s):  
Po Dong ◽  
Young-Kai Chen ◽  
Tingyi Gu ◽  
Lawrence L. Buhl ◽  
David T. Neilson ◽  
...  
Keyword(s):  
Network On Chip ◽  
Photonic Network ◽  
Silicon Photonic ◽  
On Chip

Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors

2011 ◽  
Vol 7 (2) ◽  
pp. 1-25 ◽  
Author(s):  
Aleksandr Biberman ◽  
Kyle Preston ◽  
Gilbert Hendry ◽  
Nicolás Sherwood-Droz ◽  
Johnnie Chan ◽  
...  
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Network On Chip ◽  
Photonic Network ◽  
Silicon Materials ◽  
On Chip
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