scholarly journals Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream

Author(s):  
Marcin Kowalczyk ◽  
Piotr Ciarach ◽  
Dominika Przewlocka-Rus ◽  
Hubert Szolc ◽  
Tomasz Kryjak

AbstractIn this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application – skin colour areas segmentation – on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.

2021 ◽  
Author(s):  
Marcin Kowalczyk ◽  
Tomasz Kryjak

This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the ``full'', i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.


2021 ◽  
Author(s):  
Marcin Kowalczyk ◽  
Tomasz Kryjak

This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the ``full'', i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.


Author(s):  
Daiki Matsumoto ◽  
Ryuji Hirayama ◽  
Naoto Hoshikawa ◽  
Hirotaka Nakayama ◽  
Tomoyoshi Shimobaba ◽  
...  

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