scholarly journals A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream

2021 ◽  
Author(s):  
Marcin Kowalczyk ◽  
Tomasz Kryjak
Keyword(s):  
Data Stream ◽  
Hardware Implementation ◽  
Clock Cycle ◽  
Video Stream ◽  
Connected Component ◽  
Real Time Processing ◽  
Time Processing ◽  
Evaluation Board ◽  
Labelling Method ◽  
Labelling Algorithm

This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the ``full'', i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.

scholarly journals A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream

2021 ◽  
Author(s):  
Marcin Kowalczyk ◽  
Tomasz Kryjak
Keyword(s):  
Data Stream ◽  
Hardware Implementation ◽  
Clock Cycle ◽  
Video Stream ◽  
Connected Component ◽  
Real Time Processing ◽  
Time Processing ◽  
Evaluation Board ◽  
Labelling Method ◽  
Labelling Algorithm

This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the ``full'', i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.

scholarly journals Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream

2021 ◽  
Author(s):  
Marcin Kowalczyk ◽  
Piotr Ciarach ◽  
Dominika Przewlocka-Rus ◽  
Hubert Szolc ◽  
Tomasz Kryjak
Keyword(s):  
Real Time ◽  
Hardware Implementation ◽  
Video Stream ◽  
Fpga Implementation ◽  
Connected Component ◽  
Reconfigurable Logic ◽  
Real Time Processing ◽  
Time Processing ◽  
Single Pass ◽  
4K Uhd

AbstractIn this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application – skin colour areas segmentation – on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.

Real-Time Processing for High Speed Data Stream over Large Scale Data

2012 ◽  
Vol 35 (3) ◽  
pp. 477-490 ◽  
Author(s):  
Kai-Yuan QI ◽  
Zhuo-Feng ZHAO ◽  
Jun FANG ◽  
Qiang MA
Keyword(s):  
Real Time ◽  
Data Stream ◽  
High Speed ◽  
Large Scale ◽  
Real Time Processing ◽  
Time Processing ◽  
Large Scale Data ◽  
High Speed Data ◽  
Scale Data

PARALLEL COMPUTING IN MULTIDIMENSIONAL RECURSIVE FILTERING

1993 ◽  
Vol 04 (02) ◽  
pp. 219-243 ◽  
Author(s):  
XIAOJIAN LIU ◽  
LEONARD T. BRUTON
Keyword(s):  
Hardware Implementation ◽  
Critical Path ◽  
Real Time Processing ◽  
Recursive Filtering ◽  
Time Processing ◽  
Software And Hardware ◽  
Parallel Filter ◽  
Filter Structures ◽  
Filter Algorithms ◽  
Efficient Software

This paper introduces and generalizes a number of multidimensional (MD) recursive parallel filter algorithms, which are based on the principles of orthogonal and diagonal computing, respectively. Efficient software and hardware implementation methods for the proposed parallel algorithms are presented. In particular, it is shown that systolic array implementations can be achieved for MD parallel filter structures that are locally interconnected and have a critical path of 1 multiplication plus 1 addition. In this way, the proposed parallel filters are easily able to perform real-time processing at video rates.

scholarly journals DUNE DAQ R&D integration in ProtoDUNE Single-Phase at CERN

2020 ◽  
Vol 245 ◽  
pp. 01019
Author(s):  
Roland Sipos
Keyword(s):  
Resource Utilization ◽  
Data Stream ◽  
Single Phase ◽  
Additional Data ◽  
The Self ◽  
Application Layer ◽  
Real Time Processing ◽  
Time Processing ◽  
Persistent Memory ◽  
Single Host

The DAQ system of ProtoDUNE-SP successfully proved its design principles and met the requirements of the beam run of 2018. The technical design of the DAQ system for the DUNE experiment has major differences compared to the prototype due to different requirements placed on the detector, as well as a radically different location of operation. The single-phase prototype at CERN is a major integration facility for R&D aspects of the DUNE DAQ system. The facility allows for the exploration of additional data processing capabilities and optimization of the FELIX system, which is the chosen TPC readout solution for the DUNE single-phase detectors. One of the fundamental differences from the prototype is that the DUNE DAQ relies on self-triggering. Therefore, real-time processing of the data stream for hit and trigger primitive finding is essential for the requirement of continuous readout. The supernova burst trigger requires a large and fast buffering technique, where 3D XPoint persistent memory solutions are evaluated and integrated. In order to maximize resource utilization of the FELIX hosting servers, the elimination of the 100 Gb network communication stack is desired. This implies the design and development of a single-host application layer, which is a fundamental element of the self-triggering chain. This paper discusses the evaluation and integration of these developments for the DUNE DAQ, in the ProtoDUNE environment.

scholarly journals Resolving longitudinal amplitude and phase information of two continuous data streams for high-speed and real-time processing

2009 ◽  
Vol 7 ◽  
pp. 133-137 ◽  
Author(s):  
A. Guntoro ◽  
M. Glesner
Keyword(s):  
Data Streams ◽  
Data Stream ◽  
High Speed ◽  
Hardware Implementation ◽  
Software Implementation ◽  
Phase Detector ◽  
Continuous Data ◽  
Process Data ◽  
Real Time Processing ◽  
High Speed Data

Abstract. Although there is an increase of performance in DSPs, due to its nature of execution a DSP could not perform high-speed data processing on a continuous data stream. In this paper we discuss the hardware implementation of the amplitude and phase detector and the validation block on a FPGA. Contrary to the software implementation which can only process data stream as high as 1.5 MHz, the hardware approach is 225 times faster and introduces much less latency.

Qualitative Analysis for Visual Attention of Students by Using the Technology of ICT

2021 ◽  
pp. 1-26
Author(s):  
Muhammad Farhan ◽  
Muhammad Salar Haider ◽  
N. Z. Jhanjhi ◽  
Rana Muhammad Amir Latif ◽  
Muhammad Yasir Bilal
Keyword(s):  
Machine Learning ◽  
Visual Attention ◽  
Software Package ◽  
Video Stream ◽  
Learning Tools ◽  
Eye Detection ◽  
Real Time Processing ◽  
Time Processing ◽  
Ict Tools ◽  
Attention Level

ICT tools and machine learning tools are used to analyze the visual attention of the student. The student's attention score is calculated for the analysis of the visual attention of the student. For this purpose, the authors have developed a software package (i.e., Visual Attention Tool [VAT]) based on the ICT that extracts the frames from a video stream that is taken through the webcam attached to the student's laptop. Each image is converted into a grayscale image, enhanced by image processing, then face detection is performed by following eye detection. This real-time processing of video produces a dataset by tracking the faces and eyes. It measures the attention level of the student with the timestamp. A manual observer also calculates the student's attention score focusing face and eye contact and produces a dataset manually. Then a comparative analysis of both datasets is performed in statistical and machine learning tools.

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