Real-Time FPGA Implementation of FIR Filter Using OpenCL Design

Author(s):  
Iman Firmansyah ◽  
Yoshiki Yamaguchi
2015 ◽  
Vol 5 (3) ◽  
pp. 1-10
Author(s):  
S. V. Padmajarani ◽  
◽  
M. Muralidhar ◽  

2013 ◽  
Vol 11 ◽  
pp. 191-198 ◽  
Author(s):  
Muhammad Firmansyah Kasim ◽  
Trio Adiono ◽  
Muhammad Fahreza ◽  
Muhammad Fadhli Zakiy

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.


2012 ◽  
Author(s):  
Vanishree Gopalakrishna ◽  
Nasser Kehtarnavaz ◽  
Chandrasekhar Patlolla ◽  
Matthias F. Carlsohn

2021 ◽  
Author(s):  
Xiangxiang Wei ◽  
Gao-Ming Du ◽  
Xiaolei Wang ◽  
Hongfang Cao ◽  
Shijie Hu ◽  
...  

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