The interconnection of many processors in order to increase the computing power of the ensemble is a growing theme in the data processing industry [1]. These processors may be within modules on a common board, on seperate boards within a common frame, or in seperate frames distributed in a room or building. A key element of this “computer complex” is the network which allows efficient data transfers. These data processing networks are differentiated from data communications networks by a demand for fast data transfer, so that the processors and memory at the nodes can interact in times measured in about 1–1000 machine cycles. Machine cycle times might be from tens to hundreds of nanoseconds, and the amount of data transferred might be measured in Kilobytes [2]. This implies both a fast and a high bandwidth technology for implementing these interconnections, as well as a limited link distance. The VLSI IC technology and associated dense electrical chip packaging which has made such powerful computing nodes possible, also implies a requirement for dense packaging of the optical link adapter, for compatability [3]. The multiprocessor complex has very high requirements on reliability, leading to low tolerance for component failure or erroneous data transmission. Eight year life, with failure rates less than 0.01%/Khr, and link bit error rates less than 1 in 1015 are not uncommon requirements [4]. The performance and cost of these networks are often determined by the wiring technology chosen, specifically the electronics and opto-electronics of the interfaces at the network's nodes. Optical interconnections are potentially attractive for this application, but the requirements on optical, electrical and associated packaging technologies are significantly different than the technology which has been developed for the data communications applications. [4, 5].
Secure Device Discovery in Big Data Communications Networks: Opportunities and Challenges