Fast locking technique for phase locked loop based on phase error cancellation

Author(s):  
Mohsen Karbalaei Mohammad Ali ◽  
Omid Hashemipour
2016 ◽  
Vol 10 (5) ◽  
pp. 417-422
Author(s):  
Zhaoming Ding ◽  
Haiqi Liu ◽  
Qiang Li

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  


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