Enhanced Quasi Type-1 PLL-Based Multi-Functional Control of Single-Phase Dynamic Voltage Restorer

This paper considers the reference signal generation problem for the multi-functional operation of single-phase dynamic voltage restorers. For this purpose, a single-phase quasi type-1 phase-locked loop (QT1-PLL) is proposed. The pre-loop filter part of this PLL is composed of a frequency-fixed delayed signal cancellation method and a two-stage all-pass filter. Thanks to the frequency-fixed nature, the pre-loop filter is easy to implement and can provide rejection of any measurement offset. Moreover, this PLL benefits from the excellent harmonic robustness property of the conventional QT1-PLL. Small-signal modeling and gain tuning procedures are detailed in this paper. In order to track the reference voltage signals generated by the proposed PLL, a super-twisting sliding mode controller is also presented, which helps to achieve fast dynamic responses. Laboratory-scale prototype-based experimental studies were conducted to validate the developed reference generator and the controller. Experimental results show that the proposed method is fast in detecting and compensating any grid voltage anomalies to maintain constant load voltage despite voltage sag, swell, and harmonic distortions.

A filter algorithm for receiver tracking loops assisted by inertial information

In traditional satellite navigation receivers, the parameters of tracking loop such as loop bandwidth and integration time are usually set in the design of the receivers according to different scenarios. The signal tracking performance is limited in traditional receivers. In addition, when the tracking ability of weak signals is improved by extending the integration time, negative effect of residual frequency error becomes more and more serious with extension of the integration time. To solve these problems, this paper presents out research on receiver tracking algorithms and proposes an optimised tracking algorithm with inertial information. The receiver loop filter is designed based on Kalman filter, reducing the phase jitter caused by thermal noise in the weak signal environment and improving the signal tracking sensitivity. To confirm the feasibility of the proposed algorithm, simulation tests are conducted.

Stabilization of the backward wave oscillator frequency for operation with high quality resonators

This article describes the performance of a backward wave oscillator, stabilized with phase locked loop. The backward wave oscillator is locked to the frequency of a direct digital synthesizer using an automatic phase locked loop. The direct digital synthesizer is playing the role of tuning part in the suggested frequency synthesizer. Mathematical evaluations of the stability, phase noise and locking speed of the suggested frequency synthesizer are obtained. The optimization technique of frequency synthesizers parameters is presented. This allows to get the maximum response speed and the lowest phase noise and level of spurious with fine tuning (less than 1 Hz). It was shown that the order and type of loop filter in the frequency synthesizer will affect simultaneously the response speed, phase noise and spurious level. The results of this paper shows that the frequency synthesizer can be used in small samples properties measurement using open resonators.

Residual-guided In-loop Filter Using Convolution Neural Network

The block-based coding structure in the hybrid video coding framework inevitably introduces compression artifacts such as blocking, ringing, and so on. To compensate for those artifacts, extensive filtering techniques were proposed in the loop of video codecs, which are capable of boosting the subjective and objective qualities of reconstructed videos. Recently, neural network-based filters were presented with the power of deep learning from a large magnitude of data. Though the coding efficiency has been improved from traditional methods in High-Efficiency Video Coding (HEVC), the rich features and information generated by the compression pipeline have not been fully utilized in the design of neural networks. Therefore, in this article, we propose the Residual-Reconstruction-based Convolutional Neural Network (RRNet) to further improve the coding efficiency to its full extent, where the compression features induced from bitstream in form of prediction residual are fed into the network as an additional input to the reconstructed frame. In essence, the residual signal can provide valuable information about block partitions and can aid reconstruction of edge and texture regions in a picture. Thus, more adaptive parameters can be trained to handle different texture characteristics. The experimental results show that our proposed RRNet approach presents significant BD-rate savings compared to HEVC and the state-of-the-art CNN-based schemes, indicating that residual signal plays a significant role in enhancing video frame reconstruction.

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

Sensorless Control Strategy for BLDC Motors Based on a Type-3 Phase Locked Loop

This paper presents the design procedure of a high-performance sensorless control strategy for the widely used brushless DC (BLDC) motors. Generally, conventional sensorless techniques are based on detecting the zero-crossing instants (ZCP) of the back electromotives forces (back-EMFs) of the three phases. These methods, although widely adopted and marketed on an industrial level, involve many limitations such as filtering delays, difficulty to operate at low speeds and immunity against Electromagnetic Interferences (EMI). In this paper, the main objective is to develop a sensorless control technique integrally independent from the zero-crossing points of the back-EMFs. In the proposed method, a zero-delay adaptive filter was used to extract the fundamental and the quadrature components of the line-to-line voltage of the motor. Then, the Synchronous Reference Frame Phase Locked Loop (SRF-PLL) is used to estimate the electrical angle of phase-to-phase back-EMF along with the rotor speed. The conventional SRF-PLL was implemented using a second-order loop filter (type-3 PLL) in order to improve synchronization performances and for better rejection of voltage spikes induced in motor phases during commutations. The benefits of the control technique are brought to light through simulation results. An experimental prototype was designed to confirm the validity of the proposed method.

Integer N Synthesizer Design for LoRa Transceivers

This paper presents the study and design of an Integer N synthesizer model for three LoRa ISM bands: 430 MHz 868 MHz and 915 MHz. The proposed topology is composed by two voltage controlled oscillators working in two different bands. The presented model uses the same phase-frequency detector, charge pump and loop filter. This study is focused on dynamic and steady-state analysis in order to infer the synthesizer stability and bandwidth. The performed study shows that the settling time for all bands is less than 40 µs for a bandwidth of 102 kHz.