The invention relates to an intermediate frequency power supply fast start and digital phase locked loop control technology

Intermediate frequency induction heating is widely used because of its low energy consumption and high thermal efficiency, but the speed of traditional intermediate frequency power supply is slow and its frequency tracking accuracy is limited. In order to maintain the resonant state of the load during the working process of the induction heating power supply and realize the automatic frequency tracking control during the working process. The frequency tracking of the 40kW intermediate frequency power supply is researched, and a method of combining the resonant frequency automatic identification algorithm and the digital phase locked loop frequency tracking control method is proposed. MATLAB simulation and experiment show that the system based on this control method can save the time of searching the load resonance frequency in the initial stage of the power supply, improve the frequency tracking speed, accelerate the dynamic response speed of the system, avoid the failure of frequency lock, and play the role of fast and stable startup.

ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

Switched-line network with digital phase shifter

This article studies a six-bit digital phase shifter and its compatible design through different physiognomies. Furthermore, the communication circuits are applied based on modern knowledge by application. The study started with the initial values of 5.625° as the digital phase shifter is programmed discrete and advanced to a 64-step size. Moreover, the properties of bandwidth are computed by 6.44–10.85 GHz. (C-X band) is related to the phase shifter around the frequency, so the full improvement of 66 dB of the phase shifter is 7 dB. Besides, the phase is changing in array antenna and secondhand in optimal Design. Finally, the study discusses dissimilar kinds of digital phase shifters, to study the parameters that affects the design in future cases.

On digital phase detector

A digital phase detector for processing signals with phase modulation in a wide range of changes in the phase of the received signal is considered. A block diagram of a digital detector with minimal computational costs for the signal period is proposed. The problem of phase jumps when it changes by more than 2π is solved. An estimate is obtained for the noise immunity of a phase detector when exposed to Gaussian noise. Supposed hardware implementation of a phase detector based on field-programmable gate arrays. It can be used in devices for digital processing of the angular modulation signals, devices for controlling the phase of the reference signal and in different measurers.

High Spatial-Resolution Digital Phase-Stepping Shearography

Digital phase-stepping shearography is a speckle interferometric technique that uses laser speckles to generate the phase map of the displacement derivatives of a stressed object, and hence can map the stresses of a deformed object directly. Conventional digital phase-stepping shearography relies on the use of video cameras of relatively lower resolution, in the order of 5 megapixels or lower, operating at a video rate. In the present work, we propose a novel method of performing high spatial resolution phase stepping shearography. This method uses a 24 megapixel still digital imaging device (DSLR camera) and a Michelson-type shearing arrangement with an edge-clamped, center-loaded plate. Different phase-stepping algorithms were used, and all successfully generated shearograms. The system enabled extremely high-resolution phase maps to be generated from relatively large deformations applied to the test plate. Quantitative comparison of the maximum achieved spatial resolution is made with the video-rate cameras used in conventional shearography. By switching from conventional (video) imaging methods to still imaging methods, significantly higher spatial resolution (by about 5 times) can be achieved in actual phase-stepping shearography, which is of great usefulness in industrial non-destructive testing (NDT).