Heuristic algorithms for multi-criteria hardware/software partitioning in embedded systems codesign

2020 ◽  
Vol 84 ◽  
pp. 106610 ◽  
Author(s):  
Adil Iguider ◽  
Kaouthar Bousselam ◽  
Oussama Elissati ◽  
Mouhcine Chami ◽  
Abdeslam En-Nouaary
Author(s):  
Adil Iguider ◽  
Kaouthar Bousselam ◽  
Oussama Elissati ◽  
Mouhcine Chami ◽  
Abdeslam En-Nouaary

2019 ◽  
Vol 12 (4) ◽  
pp. 111
Author(s):  
Adil Iguider ◽  
Kaouthar Bousselam ◽  
Oussama Elissati ◽  
Mouhcine Chami ◽  
Abdeslam En-Nouaary

The codesign is a robust methodology, used in modern embedded systems with the objective of achieving the functional specifications and meeting the non-functional requirements. The most interesting step in the codesing  is the process of  Hardware/Software Partitioning. The aim is to decide which functionalities of the system should be implemented in hardware ($HW$) or in software ($SW$). In this article, a new heuristic algorithm is proposed to simultaneously optimize the hardware area (cost) and the execution time (performance) of a multiprocessor system. The proposed algorithm is inspired from game theory and especially from the GO game. The system is modeled using the DAG graph (Data Acyclic Graph), and two players (HW player and SW player) play in turn and choose a block (functionality) from the graph (system). The HW player has the goal of optimizing the global HW area while the SW player has the objective of minimizing the global execution time. After the game termination, and based on the 0-1 Knapsack algorithm, a step of refinement is used to meet the constraint on the total hardware area or on the overall execution time if a constraint is pre-defined. Experimental results show that the proposed algorithm gives better solutions compared to the Simulated Annealing algorithm and the Genetic Algorithm.


2021 ◽  
Author(s):  
Abdullah Siddiqui

One of the most critical steps of embedded systems design is Hardware-Software partitioning. It is characterized by distributing the components of an application between hardware and software such that the user defined system constraints are satisfied. Heterogeneous computing platforms consisting of CPUs and GPUs have tremendous potential for enhancing the performance of embedded applications. The challenge of application partitioning for CPU-GPU mapping is much greater on such platforms due to their unique and diverse characteristics. In this thesis, an optimization algorithm is devised and presented for partitioning and mapping computational tasks on CPU-GPU platforms while keeping a check on the power consumption. Our methodology also uses parallelism in applications and their tasks by utilizing the architectural capabilities of the GPU. The optimization algorithm was tested with a MJPEG decoder, several benchmarks and synthetic graphs.


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