Fault-Tolerant Quantum Reversible Full Adder/Subtractor: Design and Implementation

Optik ◽  
2021 ◽  
pp. 168543
Author(s):  
Seyyed Mohammad Amir Mirizadeh ◽  
Parvaneh Asghari
Author(s):  
Surajit Dutta ◽  
Sudip Dutta ◽  
Riddhi Burman ◽  
Mridul Sankar Barik ◽  
Chandan Mazumdar

Mechatronics ◽  
2005 ◽  
Vol 15 (10) ◽  
pp. 1253-1272 ◽  
Author(s):  
H.K. Sung ◽  
S.H. Lee ◽  
Z. Bien

Author(s):  
Himanshu Shekhar, Prof. Deepa Gianchandani

In the complex advance microelectronics based system, handling units are managing gadgets of littler size, which are delicate to the transient faults. A framework should be fabricated that will perceive the presence of faults and fuses strategies to will endure these faults without troublesome the typical activity A transient fault happens in a circuit caused by the electromagnetic commotions, astronomical beams, crosstalk and power supply clamor. It is extremely hard to recognize these faults amid disconnected testing. Subsequently a region effective fault tolerant full adder for testing and fixing of transient and changeless faults happened in single and multi-net is proposed. Furthermore, the proposed design can likewise identify and fix perpetual faults. This structure acquires much lower equipment overheads with respect to the conventional equipment design. In this paper, talk about various fault tolerant methodology for CMOS and ICs.


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