Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology

2021 ◽  
Author(s):  
Mukesh Patidar ◽  
Namit Gupta
Keyword(s):  
Full Adder ◽  
Efficient Design ◽  
Design And Implementation

An Efficient Design and Implementation of the In-Parameter-Order Algorithm

2017 ◽  
Vol 12 (1) ◽  
pp. 51-67 ◽  
Author(s):  
Kristoffer Kleine ◽  
Dimitris E. Simos
Keyword(s):  
Efficient Design ◽  
Design And Implementation ◽  
Order Algorithm

scholarly journals Analysis of Area-Efficiency vs. Unrolling for eSTREAM Hardware Portfolio Stream Ciphers

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1935
Author(s):  
Fares Alharbi ◽  
Muhammad Khurram Hameed ◽  
Anusha Chowdhury ◽  
Ayesha Khalid ◽  
Anupam Chattopadhyay ◽  
...  
Keyword(s):  
Internet Of Things ◽  
Theoretical Prediction ◽  
High Performance ◽  
Stream Ciphers ◽  
Limited Resources ◽  
Efficient Design ◽  
Low Resource ◽  
Area Efficiency ◽  
Design And Implementation ◽  
Xilinx Fpga

The demand for low resource devices has increased rapidly due to the advancements in Internet-of-things applications. These devices operate in environments that have limited resources. To ensure security, stream ciphers are implemented on hardware due to their speed and simplicity. Amongst different stream ciphers, the eSTREAM ciphers stand due to their frugal implementations. This work probes the effect of unrolling on the efficiency of eSTREAM ciphers, including Trivium, Grain (Grain 80 and Grain 128) and MICKEY (MICKEY 2.0 and MICKEY-128 2.0). It addresses the question of optimal unrolling for designing high-performance stream ciphers. The increase in the area consumption is also bench-marked. The analysis is conducted to identify efficient design principles for ciphers. We experimentally show that the resulting performance after unrolling may disagree with the theoretical prediction when the effects of technology library are considered. We report pre-layout synthesis results on 65 and 130 nm ASIC technology as well as synthesis results for Xilinx FPGA platform in support of our claim. Based on our findings, cipher design and implementation suggestions are proposed to aid hardware designers. Furthermore, we explore why and where area-efficiency for these ciphers saturate.

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