Erratum to “Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm” [Image and Vision Computing 23 (2005) 1009–1017]

2007 ◽  
Vol 25 (6) ◽  
pp. 1032
Author(s):  
Si Mahmoud Karabernou ◽  
Lounis Kessal ◽  
Fayçal Terranti
Keyword(s):  
Real Time ◽  
Hough Transform ◽  
Fpga Implementation ◽  
Cordic Algorithm

Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm

2005 ◽  
Vol 23 (11) ◽  
pp. 1009-1017 ◽  
Author(s):  
Si Mahmoud Karabernou ◽  
Fayçal Terranti
Keyword(s):  
Real Time ◽  
Hough Transform ◽  
Fpga Implementation ◽  
Cordic Algorithm

Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

2018 ◽  
Vol 12 (10) ◽  
pp. 1753-1761 ◽  
Author(s):  
Vineet Kumar ◽  
Abhijit Asati ◽  
Anu Gupta
Keyword(s):  
Hough Transform ◽  
Fpga Implementation ◽  
Memory Efficient

scholarly journals Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

2012 ◽  
Vol 2012 ◽  
pp. 1-8 ◽  
Author(s):  
Supriya Aggarwal ◽  
Kavita Khare
Keyword(s):  
Spectral Analysis ◽  
Fpga Implementation ◽  
Coordinate Space ◽  
Cordic Algorithm ◽  
Scale Free ◽  
Window Functions

One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper.

FPGA Implementation of the Generalized Hough Transform

2009 ◽  
Author(s):  
Sergio Rubén Geninatti ◽  
José Ignacio Benavides Benítez ◽  
Manuel Hernández Calviño ◽  
Nicolás Guil Mata ◽  
Juan Gómez Luna
Keyword(s):  
Hough Transform ◽  
Fpga Implementation ◽  
Generalized Hough Transform
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